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util: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230823065335.1919380-3-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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13 changed files with 18 additions and 18 deletions
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@ -1,6 +1,6 @@
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Host specific cpu indentification for x86.
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* Host specific cpu identification for x86.
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*/
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#include "qemu/osdep.h"
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@ -74,7 +74,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
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* of their memory operands to be 16-byte aligned.
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*
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* AMD has provided an even stronger guarantee that processors
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* with AVX provide 16-byte atomicity for all cachable,
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* with AVX provide 16-byte atomicity for all cacheable,
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* naturally aligned single loads and stores, e.g. MOVDQU.
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*
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* See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
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