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target/xtensa: add DFPU registers and opcodes

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DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA
does not specify how single-precision values are stored in 64-bit
registers. Existing implementations store them in the low half of the
registers.
Add value extraction and write back to single-precision opcodes.
Add new double precision opcodes. Add 64-bit register file.
Add 64-bit values dumping to the xtensa_cpu_dump_state.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2020-06-30 19:27:02 -07:00
parent de6b55cbda
commit cfa9f05181
6 changed files with 1424 additions and 45 deletions
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1
target/xtensa/overlay_tool.h
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@ -538,6 +538,7 @@
.ndepc = (XCHAL_XEA_VERSION >= 2), \
.inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
.max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
.use_first_nan = !XCHAL_HAVE_DFPU, \
EXCEPTIONS_SECTION, \
INTERRUPTS_SECTION, \
TLB_SECTION, \