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CRIS: Improve TLB management and handle delayslots at page boundaries.
* Dont flush the entire qemu tlb when the $pid changes. Instead we go through the guests TLB and choose entries that need to be flushed. * Add env->dslot and handle delayslots at pageboundaries. * Remove some unused code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
3bd8c5e4f1
commit
cf1d97f074
8 changed files with 194 additions and 138 deletions
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@ -21,8 +21,7 @@
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/*
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* FIXME:
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* The condition code translation is in desperate need of attention. It's slow
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* and for system simulation it seems buggy. It sucks.
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* The condition code translation is in need of attention.
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*/
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#include <stdarg.h>
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@ -40,13 +39,6 @@
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#include "crisv32-decode.h"
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#include "qemu-common.h"
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#define CRIS_STATS 0
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#if CRIS_STATS
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#define STATS(x) x
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#else
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#define STATS(x)
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#endif
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#define DISAS_CRIS 0
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#if DISAS_CRIS
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#define DIS(x) x
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@ -109,25 +101,18 @@ typedef struct DisasContext {
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int user; /* user or kernel mode. */
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int is_jmp;
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int dyn_jmp;
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uint32_t delayed_pc;
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int delayed_branch;
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int bcc;
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uint32_t condlabel;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext;
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void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
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static void gen_BUG(DisasContext *dc, char *file, int line)
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{
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printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
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fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
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cpu_dump_state (dc->env, stdout, fprintf, 0);
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fflush(NULL);
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cris_prepare_jmp (dc, 0x70000000 + line);
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cpu_abort(dc->env, "%s:%d\n", file, line);
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}
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const char *regnames[] =
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@ -207,7 +192,7 @@ static inline void t_gen_mov_TN_preg(TCGv tn, int r)
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else
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tcg_gen_mov_tl(tn, cpu_PR[r]);
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}
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static inline void t_gen_mov_preg_TN(int r, TCGv tn)
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static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
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{
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if (r < 0 || r > 15)
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fprintf(stderr, "wrong register write $p%d\n", r);
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@ -216,10 +201,9 @@ static inline void t_gen_mov_preg_TN(int r, TCGv tn)
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else if (r == PR_SRS)
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tcg_gen_andi_tl(cpu_PR[r], tn, 3);
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else {
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if (r == PR_PID) {
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tcg_gen_helper_0_0(helper_tlb_flush);
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}
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tcg_gen_mov_tl(cpu_PR[r], tn);
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if (r == PR_PID)
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tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
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}
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}
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@ -596,7 +580,7 @@ static inline void t_gen_swapr(TCGv d, TCGv s)
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tcg_gen_discard_tl(org_s);
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}
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static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
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static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
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{
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TCGv btaken;
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int l1;
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@ -606,9 +590,9 @@ static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
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/* Conditional jmp. */
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t_gen_mov_TN_env(btaken, btaken);
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tcg_gen_movi_tl(env_pc, pc_false);
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tcg_gen_mov_tl(env_pc, pc_false);
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tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
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tcg_gen_movi_tl(env_pc, pc_true);
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tcg_gen_mov_tl(env_pc, pc_true);
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gen_set_label(l1);
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tcg_gen_discard_tl(btaken);
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@ -740,10 +724,11 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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int writeback = 1;
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if (dc->update_cc) {
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cris_update_cc_op(dc, op, size);
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tcg_gen_mov_tl(cc_dest, cpu_T[0]);
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if (op != CC_OP_MOVE)
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tcg_gen_mov_tl(cc_dest, cpu_T[0]);
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/* FIXME: This shouldn't be needed. But we don't pass the
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tests without it. Investigate. */
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tests without it. Investigate. */
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t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
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t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
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}
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@ -812,7 +797,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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TCGv mof;
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mof = tcg_temp_new(TCG_TYPE_TL);
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t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
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t_gen_mov_preg_TN(PR_MOF, mof);
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t_gen_mov_preg_TN(dc, PR_MOF, mof);
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tcg_gen_discard_tl(mof);
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}
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break;
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@ -821,7 +806,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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TCGv mof;
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mof = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
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t_gen_mov_preg_TN(PR_MOF, mof);
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t_gen_mov_preg_TN(dc, PR_MOF, mof);
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tcg_gen_discard_tl(mof);
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}
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break;
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@ -875,12 +860,6 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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}
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if (dc->update_cc)
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tcg_gen_mov_tl(cc_result, cpu_T[0]);
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{
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/* TODO: Optimize this. */
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if (!dc->flagx_live)
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cris_evaluate_flags(dc);
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}
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}
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static int arith_cc(DisasContext *dc)
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@ -1073,7 +1052,6 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
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break;
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case CC_A:
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cris_evaluate_flags(dc);
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tcg_gen_movi_tl(cpu_T[0], 1);
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break;
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default:
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@ -1087,14 +1065,13 @@ static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->delayed_pc = dc->pc + offset;
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dc->bcc = cond;
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if (cond != CC_A)
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{
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gen_tst_cc (dc, cond);
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t_gen_mov_env_TN(btaken, cpu_T[0]);
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}
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tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
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} else
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t_gen_mov_env_TN(btaken, tcg_const_tl(1));
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tcg_gen_movi_tl(env_btarget, dc->pc + offset);
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}
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@ -1104,18 +1081,7 @@ void cris_prepare_dyn_jmp (DisasContext *dc)
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->dyn_jmp = 1;
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dc->bcc = CC_A;
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}
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void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
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{
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->delayed_pc = dst;
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dc->dyn_jmp = 0;
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dc->bcc = CC_A;
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t_gen_mov_env_TN(btaken, tcg_const_tl(1));
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}
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void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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@ -1123,6 +1089,7 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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{
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int mem_index = cpu_mmu_index(dc->env);
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cris_evaluate_flags(dc);
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if (size == 1) {
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if (sign)
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tcg_gen_qemu_ld8s(dst, addr, mem_index);
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@ -1236,10 +1203,7 @@ static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
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t_gen_zext(cpu_T[0], cpu_R[rd], size);
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}
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/* Prepare T0 and T1 for a memory + alu operation.
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s_ext decides if the operand1 should be sign-extended or zero-extended when
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needed. */
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static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
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static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize)
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{
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unsigned int rs, rd;
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uint32_t imm;
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@ -1272,7 +1236,7 @@ static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
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imm = ldl_code(dc->pc + 2);
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DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
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imm, rd, s_ext, memsize));
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imm, rd, s_ext, memsize));
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tcg_gen_movi_tl(cpu_T[1], imm);
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dc->postinc = 0;
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} else {
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@ -1282,9 +1246,20 @@ static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
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else
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t_gen_zext(cpu_T[1], cpu_T[1], memsize);
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}
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return insn_len;
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}
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/* Prepare T0 and T1 for a memory + alu operation.
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s_ext decides if the operand1 should be sign-extended or zero-extended when
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needed. */
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static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
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{
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int insn_len;
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insn_len = dec_prep_move_m(dc, s_ext, memsize);
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/* put dest in T0. */
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t_gen_mov_TN_reg(cpu_T[0], rd);
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tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
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return insn_len;
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}
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@ -1421,7 +1396,7 @@ static unsigned int dec_btstq(DisasContext *dc)
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crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
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t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
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dc->flags_live = 1;
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return 2;
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}
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@ -1702,7 +1677,9 @@ static char * swapmode_name(int mode, char *modename) {
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static unsigned int dec_swap_r(DisasContext *dc)
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{
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DIS(char modename[4]);
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#if DISAS_CRIS
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char modename[4];
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#endif
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DIS(fprintf (logfile, "swap%s $r%u\n",
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swapmode_name(dc->op2, modename), dc->op1));
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@ -1777,7 +1754,7 @@ static unsigned int dec_btst_r(DisasContext *dc)
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crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
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t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
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dc->flags_live = 1;
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return 2;
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}
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@ -1900,14 +1877,16 @@ static unsigned int dec_setclrf(DisasContext *dc)
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flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
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| EXTRACT_FIELD(dc->ir, 0, 3);
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DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
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if (set && flags == 0)
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if (set && flags == 0) {
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DIS(fprintf (logfile, "nop\n"));
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else if (!set && (flags & 0x20))
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} else if (!set && (flags & 0x20)) {
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DIS(fprintf (logfile, "di\n"));
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else
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}
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else {
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DIS(fprintf (logfile, "%sf %x\n",
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set ? "set" : "clr",
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set ? "set" : "clr",
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flags));
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}
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if (set && (flags & X_FLAG)) {
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dc->flagx_live = 1;
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@ -1924,7 +1903,7 @@ static unsigned int dec_setclrf(DisasContext *dc)
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/* Enter user mode. */
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t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
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tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
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dc->is_jmp = DISAS_UPDATE;
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dc->is_jmp = DISAS_NEXT;
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}
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tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
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}
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@ -1971,7 +1950,7 @@ static unsigned int dec_move_rp(DisasContext *dc)
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else
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
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t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
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if (dc->op2 == PR_CCS) {
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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dc->flags_live = 1;
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@ -2004,7 +1983,7 @@ static unsigned int dec_move_mr(DisasContext *dc)
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dc->op1, dc->postinc ? "+]" : "]",
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dc->op2));
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insn_len = dec_prep_alu_m(dc, 0, memsize);
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insn_len = dec_prep_move_m(dc, 0, memsize);
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cris_cc_mask(dc, CC_MASK_NZ);
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crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
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do_postinc(dc, memsize);
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@ -2317,7 +2296,7 @@ static unsigned int dec_move_mp(DisasContext *dc)
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}
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}
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t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
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t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
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do_postinc(dc, memsize);
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return insn_len;
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@ -2337,7 +2316,6 @@ static unsigned int dec_move_pm(DisasContext *dc)
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if (dc->op2 == PR_CCS)
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cris_evaluate_flags(dc);
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t_gen_mov_TN_preg(cpu_T[1], dc->op2);
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gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
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cris_cc_mask(dc, 0);
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@ -2482,7 +2460,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
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cris_cc_mask(dc, 0);
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/* Store the return address in Pd. */
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tcg_gen_movi_tl(env_btarget, imm);
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t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
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t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
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cris_prepare_dyn_jmp(dc);
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return 6;
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}
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@ -2499,7 +2477,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
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tcg_gen_movi_tl(cpu_T[0], imm);
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tcg_gen_mov_tl(env_btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
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t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
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t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
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cris_prepare_dyn_jmp(dc);
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return 6;
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}
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@ -2512,7 +2490,7 @@ static unsigned int dec_jasc_r(DisasContext *dc)
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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tcg_gen_mov_tl(env_btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
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t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
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t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
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cris_prepare_dyn_jmp(dc);
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return 2;
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}
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@ -2547,7 +2525,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
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tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
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tcg_gen_mov_tl(env_btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
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t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
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t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
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cris_prepare_dyn_jmp(dc);
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return 6;
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}
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@ -2563,7 +2541,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
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tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
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tcg_gen_mov_tl(env_btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
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||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
return 6;
|
||||
}
|
||||
|
|
@ -2785,8 +2763,42 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Delay slots on QEMU/CRIS.
|
||||
*
|
||||
* If an exception hits on a delayslot, the core will let ERP (the Exception
|
||||
* Return Pointer) point to the branch (the previous) insn and set the lsb to
|
||||
* to give SW a hint that the exception actually hit on the dslot.
|
||||
*
|
||||
* CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
|
||||
* the core and any jmp to an odd addresses will mask off that lsb. It is
|
||||
* simply there to let sw know there was an exception on a dslot.
|
||||
*
|
||||
* When the software returns from an exception, the branch will re-execute.
|
||||
* On QEMU care needs to be taken when a branch+delayslot sequence is broken
|
||||
* and the branch and delayslot dont share pages.
|
||||
*
|
||||
* The TB contaning the branch insn will set up env->btarget and evaluate
|
||||
* env->btaken. When the translation loop exits we will note that the branch
|
||||
* sequence is broken and let env->dslot be the size of the branch insn (those
|
||||
* vary in length).
|
||||
*
|
||||
* The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
|
||||
* set). It will also expect to have env->dslot setup with the size of the
|
||||
* delay slot so that env->pc - env->dslot point to the branch insn. This TB
|
||||
* will execute the dslot and take the branch, either to btarget or just one
|
||||
* insn ahead.
|
||||
*
|
||||
* When exceptions occur, we check for env->dslot in do_interrupt to detect
|
||||
* broken branch sequences and setup $erp accordingly (i.e let it point to the
|
||||
* branch and set lsb). Then env->dslot gets cleared so that the exception
|
||||
* handler can enter. When returning from exceptions (jump $erp) the lsb gets
|
||||
* masked off and we will reexecute the branch insn.
|
||||
*
|
||||
*/
|
||||
|
||||
/* generate intermediate code for basic block 'tb'. */
|
||||
struct DisasContext ctx;
|
||||
static int
|
||||
gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
int search_pc)
|
||||
|
|
@ -2795,6 +2807,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
uint32_t pc_start;
|
||||
unsigned int insn_len;
|
||||
int j, lj;
|
||||
struct DisasContext ctx;
|
||||
struct DisasContext *dc = &ctx;
|
||||
uint32_t next_page_start;
|
||||
|
||||
|
|
@ -2803,8 +2816,6 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
|
||||
/* Odd PC indicates that branch is rexecuting due to exception in the
|
||||
* delayslot, like in real hw.
|
||||
* FIXME: we need to handle the case were the branch and the insn in
|
||||
* the delayslot do not share pages.
|
||||
*/
|
||||
pc_start = tb->pc & ~1;
|
||||
dc->env = env;
|
||||
|
|
@ -2820,19 +2831,24 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
dc->flagx_live = 0;
|
||||
dc->flags_x = 0;
|
||||
dc->cc_mask = 0;
|
||||
dc->update_cc = 0;
|
||||
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
|
||||
|
||||
dc->user = env->pregs[PR_CCS] & U_FLAG;
|
||||
dc->delayed_branch = 0;
|
||||
/* Decode TB flags. */
|
||||
dc->user = tb->flags & U_FLAG;
|
||||
dc->delayed_branch = !!(tb->flags & 7);
|
||||
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||
fprintf(logfile,
|
||||
"search=%d pc=%x ccs=%x pid=%x usp=%x dbg=%x %x %x\n"
|
||||
"srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
|
||||
"pid=%x usp=%x dbg=%x %x %x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n",
|
||||
search_pc, env->pc, env->pregs[PR_CCS],
|
||||
search_pc, dc->pc, dc->ppc,
|
||||
env->btarget, tb->flags & 7,
|
||||
env->pregs[PR_CCS],
|
||||
env->pregs[PR_PID], env->pregs[PR_USP],
|
||||
env->debug1, env->debug2, env->debug3,
|
||||
env->regs[0], env->regs[1], env->regs[2], env->regs[3],
|
||||
|
|
@ -2860,14 +2876,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
while (lj < j)
|
||||
gen_opc_instr_start[lj++] = 0;
|
||||
}
|
||||
if (dc->delayed_branch == 1) {
|
||||
if (dc->delayed_branch == 1)
|
||||
gen_opc_pc[lj] = dc->ppc | 1;
|
||||
gen_opc_instr_start[lj] = 0;
|
||||
}
|
||||
else {
|
||||
else
|
||||
gen_opc_pc[lj] = dc->pc;
|
||||
gen_opc_instr_start[lj] = 1;
|
||||
}
|
||||
gen_opc_instr_start[lj] = 1;
|
||||
}
|
||||
|
||||
/* Pretty disas. */
|
||||
DIS(fprintf(logfile, "%x ", dc->pc));
|
||||
if (search_pc) {
|
||||
DIS(fprintf(logfile, "%x ", dc->pc));
|
||||
}
|
||||
|
||||
dc->clear_x = 1;
|
||||
|
|
@ -2881,17 +2900,13 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
actually genereating any host code, the simulator will just
|
||||
loop doing nothing for on this program location. */
|
||||
if (dc->delayed_branch) {
|
||||
t_gen_mov_env_TN(dslot, tcg_const_tl(0));
|
||||
dc->delayed_branch--;
|
||||
if (dc->delayed_branch == 0)
|
||||
{
|
||||
if (dc->bcc == CC_A) {
|
||||
tcg_gen_mov_tl(env_pc, env_btarget);
|
||||
dc->is_jmp = DISAS_JUMP;
|
||||
}
|
||||
else {
|
||||
t_gen_cc_jmp(dc->delayed_pc, dc->pc);
|
||||
dc->is_jmp = DISAS_JUMP;
|
||||
}
|
||||
t_gen_cc_jmp(env_btarget,
|
||||
tcg_const_tl(dc->pc));
|
||||
dc->is_jmp = DISAS_JUMP;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2900,15 +2915,16 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
if (!(tb->pc & 1) && env->singlestep_enabled)
|
||||
break;
|
||||
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
|
||||
&& ((dc->pc < next_page_start) || dc->delayed_branch));
|
||||
&& (dc->pc < next_page_start));
|
||||
|
||||
/* Broken branch+delayslot sequence. */
|
||||
if (dc->delayed_branch == 1) {
|
||||
/* Reexecute the last insn. */
|
||||
dc->pc = dc->ppc | 1;
|
||||
/* Set env->dslot to the size of the branch insn. */
|
||||
t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
|
||||
}
|
||||
|
||||
if (!dc->is_jmp) {
|
||||
D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
|
||||
D(fprintf(logfile, "!jmp pc=%x jmp=%d db=%d\n", dc->pc,
|
||||
dc->is_jmp, dc->delayed_branch));
|
||||
/* T0 and env_pc should hold the new pc. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
|
|
@ -3079,6 +3095,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
|
|||
TCG_HELPER(helper_dummy);
|
||||
|
||||
TCG_HELPER(helper_tlb_flush);
|
||||
TCG_HELPER(helper_tlb_flush_pid);
|
||||
TCG_HELPER(helper_movl_sreg_reg);
|
||||
TCG_HELPER(helper_movl_reg_sreg);
|
||||
TCG_HELPER(helper_rfe);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue