mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-08 02:03:56 -06:00
aspeed queue:
* Fixed GPIO interrupt status when in index mode * Added GPIO support for the AST2700 SoC and specific test cases * Fixed crypto controller (HACE) Accumulative hash function * Converted Aspeed machine avocado tests to the new functional framework. SDK tests still to be addressed. * Fixed issue in the SSI controller when doing writes in user mode * Added support for the WRSR2 register of Winbond flash devices * Added SFDP table for the Windbond w25q80bl flash device * Changed flash device models for the ast1030-a1 EVB -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ6MIACgkQUaNDx8/7 7KFQPA//RTxi1PmCDlzd1ffzMWEadD3CpGLJ4RgEeZpNtkx6IF2uFFBdlNgjTSmD B8FdIOVb8qo2omXahKIVIgoKbGgn3U3jciH67D/x4Jyp8IhW6n5XwZzKNJ7kLVHX IluGmlvqNumSKl3vxsLvprC0ojRiO/SfWkzS6VOwoFPM7uNDTybQicWBBoy3Jh3e VVlMwIeKHMQVJGpI8PQbtnFZO4HaMqWwlo0EoIJji59fdyWULLvrXzH9YhzwFVjQ oCNvJUBLfxLse7c13cm/LuNmw+IQtLC5OztsOOtv1XZ1MruhJ7t316eGsQEpeWcD Yy5RK4mIBJMExu9oxcKOqgSznQSgenvNGWg6Z9FyyKGciylafnE8GeT35WObumyD v9gzgeLcw5DgvDgQXaYi4IkKyezaHoE3HPbFdBEZHBt8tn5pPGmXM0lEWL5xQ5B8 h6HphjxIlFxeHIxYenLJowLBMOt8aFXzGboF2XCLrx19OC2zvoo7klCbFeAfZpvQ JMXP+GsQIe7fnBMbyXGrJh9q+/7tKR4ivtTV/vnSF0FPtyzxdoSrYsUA4SZqSWvI ONz62p+zlE/oXBUIaFnC2Ea41YwJ7mDbmcSU1dFxmE0xRVmoYlUocoeS2VOUmTH0 CMgEcmMXQG0vx8nipQbScbuWRCBlf0YwJ7Y7stgI8HabmsMMbIg= =DqCH -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu into staging aspeed queue: * Fixed GPIO interrupt status when in index mode * Added GPIO support for the AST2700 SoC and specific test cases * Fixed crypto controller (HACE) Accumulative hash function * Converted Aspeed machine avocado tests to the new functional framework. SDK tests still to be addressed. * Fixed issue in the SSI controller when doing writes in user mode * Added support for the WRSR2 register of Winbond flash devices * Added SFDP table for the Windbond w25q80bl flash device * Changed flash device models for the ast1030-a1 EVB # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ6MIACgkQUaNDx8/7 # 7KFQPA//RTxi1PmCDlzd1ffzMWEadD3CpGLJ4RgEeZpNtkx6IF2uFFBdlNgjTSmD # B8FdIOVb8qo2omXahKIVIgoKbGgn3U3jciH67D/x4Jyp8IhW6n5XwZzKNJ7kLVHX # IluGmlvqNumSKl3vxsLvprC0ojRiO/SfWkzS6VOwoFPM7uNDTybQicWBBoy3Jh3e # VVlMwIeKHMQVJGpI8PQbtnFZO4HaMqWwlo0EoIJji59fdyWULLvrXzH9YhzwFVjQ # oCNvJUBLfxLse7c13cm/LuNmw+IQtLC5OztsOOtv1XZ1MruhJ7t316eGsQEpeWcD # Yy5RK4mIBJMExu9oxcKOqgSznQSgenvNGWg6Z9FyyKGciylafnE8GeT35WObumyD # v9gzgeLcw5DgvDgQXaYi4IkKyezaHoE3HPbFdBEZHBt8tn5pPGmXM0lEWL5xQ5B8 # h6HphjxIlFxeHIxYenLJowLBMOt8aFXzGboF2XCLrx19OC2zvoo7klCbFeAfZpvQ # JMXP+GsQIe7fnBMbyXGrJh9q+/7tKR4ivtTV/vnSF0FPtyzxdoSrYsUA4SZqSWvI # ONz62p+zlE/oXBUIaFnC2Ea41YwJ7mDbmcSU1dFxmE0xRVmoYlUocoeS2VOUmTH0 # CMgEcmMXQG0vx8nipQbScbuWRCBlf0YwJ7Y7stgI8HabmsMMbIg= # =DqCH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Oct 2024 07:27:14 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu: test/qtest/aspeed_smc-test: Fix coding style hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB. hw/block/m25p80: Add SFDP table for w25q80bl flash hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq hw/block:m25p80: Fix coding style aspeed/smc: Fix write incorrect data into flash in user mode tests/functional: Convert most Aspeed machine tests hw/misc/aspeed_hace: Fix SG Accumulative hashing tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700 aspeed/soc: Support GPIO for AST2700 aspeed/soc: Correct GPIO irq 130 for AST2700 hw/gpio/aspeed: Add AST2700 support hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode hw/gpio/aspeed: Support different memory region ops hw/gpio/aspeed: Support to set the different memory size hw/gpio/aspeed: Fix coding style Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
cea8ac7854
18 changed files with 1001 additions and 381 deletions
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@ -353,7 +353,8 @@ static void test_read_page_mem(void)
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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/* Enable 4BYTE mode for controller. This is should be strapped by
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/*
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* Enable 4BYTE mode for controller. This is should be strapped by
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* HW for CE0 anyhow.
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*/
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spi_ce_ctrl(1 << CRTL_EXTENDED0);
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@ -394,7 +395,8 @@ static void test_write_page_mem(void)
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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/* Enable 4BYTE mode for controller. This is should be strapped by
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/*
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* Enable 4BYTE mode for controller. This is should be strapped by
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* HW for CE0 anyhow.
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*/
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spi_ce_ctrl(1 << CRTL_EXTENDED0);
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95
tests/qtest/ast2700-gpio-test.c
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95
tests/qtest/ast2700-gpio-test.c
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@ -0,0 +1,95 @@
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/*
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* QTest testcase for the ASPEED AST2700 GPIO Controller.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Copyright (C) 2024 ASPEED Technology Inc.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "qapi/qmp/qdict.h"
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#include "libqtest-single.h"
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#define AST2700_GPIO_BASE 0x14C0B000
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#define GPIOA0_CONTROL 0x180
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static void test_output_pins(const char *machine, const uint32_t base)
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{
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QTestState *s = qtest_init(machine);
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uint32_t offset = 0;
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uint32_t value = 0;
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uint32_t pin = 0;
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for (char c = 'A'; c <= 'D'; c++) {
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for (int i = 0; i < 8; i++) {
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offset = base + (pin * 4);
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/* output direction and output hi */
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qtest_writel(s, offset, 0x00000003);
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value = qtest_readl(s, offset);
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g_assert_cmphex(value, ==, 0x00000003);
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/* output direction and output low */
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qtest_writel(s, offset, 0x00000002);
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value = qtest_readl(s, offset);
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g_assert_cmphex(value, ==, 0x00000002);
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pin++;
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}
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}
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qtest_quit(s);
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}
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static void test_input_pins(const char *machine, const uint32_t base)
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{
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QTestState *s = qtest_init(machine);
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char name[16];
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uint32_t offset = 0;
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uint32_t value = 0;
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uint32_t pin = 0;
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for (char c = 'A'; c <= 'D'; c++) {
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for (int i = 0; i < 8; i++) {
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sprintf(name, "gpio%c%d", c, i);
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offset = base + (pin * 4);
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/* input direction */
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qtest_writel(s, offset, 0);
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/* set input */
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qtest_qom_set_bool(s, "/machine/soc/gpio", name, true);
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value = qtest_readl(s, offset);
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g_assert_cmphex(value, ==, 0x00002000);
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/* clear input */
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qtest_qom_set_bool(s, "/machine/soc/gpio", name, false);
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value = qtest_readl(s, offset);
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g_assert_cmphex(value, ==, 0);
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pin++;
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}
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}
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qtest_quit(s);
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}
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static void test_2700_input_pins(void)
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{
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test_input_pins("-machine ast2700-evb",
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AST2700_GPIO_BASE + GPIOA0_CONTROL);
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}
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static void test_2700_output_pins(void)
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{
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test_output_pins("-machine ast2700-evb",
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AST2700_GPIO_BASE + GPIOA0_CONTROL);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/ast2700/gpio/input_pins", test_2700_input_pins);
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qtest_add_func("/ast2700/gpio/output_pins", test_2700_output_pins);
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return g_test_run();
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}
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@ -210,6 +210,8 @@ qtests_aspeed = \
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['aspeed_hace-test',
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'aspeed_smc-test',
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'aspeed_gpio-test']
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qtests_aspeed64 = \
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['ast2700-gpio-test']
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qtests_stm32l4x5 = \
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['stm32l4x5_exti-test',
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@ -248,6 +250,7 @@ qtests_aarch64 = \
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(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test', 'bcm2835-i2c-test'] : []) + \
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(config_all_accel.has_key('CONFIG_TCG') and \
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config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
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(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \
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['arm-cpu-features',
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'numa-test',
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'boot-serial-test',
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