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target/riscv: add support for Zcmt extension

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Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:14:00 +08:00 • committed by Alistair Francis
parent 193eb522e4
commit ce3af0bbbc
9 changed files with 157 additions and 5 deletions
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19
target/riscv/machine.c
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@ -329,6 +329,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
}
};
static bool jvt_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
return cpu->cfg.ext_zcmt;
}
static const VMStateDescription vmstate_jvt = {
.name = "cpu/jvt",
.version_id = 1,
.minimum_version_id = 1,
.needed = jvt_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.jvt, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 7,
@ -395,6 +413,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_envcfg,
&vmstate_debug,
&vmstate_smstateen,
&vmstate_jvt,
NULL
}
};