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target/riscv: add support for Zcmt extension

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Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:14:00 +08:00 • committed by Alistair Francis
parent 193eb522e4
commit ce3af0bbbc
9 changed files with 157 additions and 5 deletions
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28
target/riscv/insn_trans/trans_rvzce.c.inc
View file

@ -1,5 +1,5 @@
/*
* RISC-V translation routines for the Zc[b,mp] Standard Extensions.
* RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions.
*
* Copyright (c) 2021-2022 PLCT Lab
*
@ -26,6 +26,11 @@
return false; \
} while (0)
#define REQUIRE_ZCMT(ctx) do { \
if (!ctx->cfg_ptr->ext_zcmt) \
return false; \
} while (0)
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
{
REQUIRE_ZCB(ctx);
@ -283,3 +288,24 @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a)
return true;
}
static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
{
REQUIRE_ZCMT(ctx);
/*
* Update pc to current for the non-unwinding exception
* that might come from cpu_ld*_code() in the helper.
*/
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
}
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}