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hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit

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Implement a model of the Message Handling Unit (MHU) found in
the Arm SSE-200. This is a simple device which just contains
some registers which allow the two cores of the SSE-200
to raise interrupts on each other.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-02-28 10:55:15 +00:00
parent adf2e451f3
commit cdf63440ea
6 changed files with 250 additions and 0 deletions
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include/hw/misc/armsse-mhu.h Normal file
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/*
* ARM SSE-200 Message Handling Unit (MHU)
*
* Copyright (c) 2019 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the Message Handling Unit (MHU) which is part of the
* Arm SSE-200 and documented in
* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
*
* QEMU interface:
* + sysbus MMIO region 0: the system information register bank
* + sysbus IRQ 0: interrupt for CPU 0
* + sysbus IRQ 1: interrupt for CPU 1
*/
#ifndef HW_MISC_SSE_MHU_H
#define HW_MISC_SSE_MHU_H
#include "hw/sysbus.h"
#define TYPE_ARMSSE_MHU "armsse-mhu"
#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
typedef struct ARMSSEMHU {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq cpu0irq;
qemu_irq cpu1irq;
uint32_t cpu0intr;
uint32_t cpu1intr;
} ARMSSEMHU;
#endif