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target/riscv: Make PMP region count configurable
Previously, the number of PMP regions was hardcoded to 16 in QEMU. This patch replaces the fixed value with a new `pmp_regions` field, allowing platforms to configure the number of PMP regions. If no specific value is provided, the default number of PMP regions remains 16 to preserve the existing behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250606072525.17313-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Jay Chang
Alistair Francis
parent
b0175841fa
commit
cd633bea8b
6 changed files with 74 additions and 14 deletions
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@ -1119,6 +1119,7 @@ static void riscv_cpu_init(Object *obj)
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cpu->cfg.cbom_blocksize = 64;
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cpu->cfg.cbop_blocksize = 64;
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cpu->cfg.cboz_blocksize = 64;
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cpu->cfg.pmp_regions = 16;
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cpu->env.vext_ver = VEXT_VERSION_1_00_0;
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cpu->cfg.max_satp_mode = -1;
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@ -1563,6 +1564,46 @@ static const PropertyInfo prop_pmp = {
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.set = prop_pmp_set,
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};
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static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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uint8_t value;
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visit_type_uint8(v, name, &value, errp);
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if (cpu->cfg.pmp_regions != value && riscv_cpu_is_vendor(obj)) {
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cpu_set_prop_err(cpu, name, errp);
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return;
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}
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if (cpu->env.priv_ver < PRIV_VERSION_1_12_0 && value > OLD_MAX_RISCV_PMPS) {
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error_setg(errp, "Number of PMP regions exceeds maximum available");
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return;
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} else if (value > MAX_RISCV_PMPS) {
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error_setg(errp, "Number of PMP regions exceeds maximum available");
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return;
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}
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cpu_option_add_user_setting(name, value);
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cpu->cfg.pmp_regions = value;
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}
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static void prop_num_pmp_regions_get(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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uint8_t value = RISCV_CPU(obj)->cfg.pmp_regions;
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visit_type_uint8(v, name, &value, errp);
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}
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static const PropertyInfo prop_num_pmp_regions = {
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.type = "uint8",
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.description = "num-pmp-regions",
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.get = prop_num_pmp_regions_get,
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.set = prop_num_pmp_regions_set,
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};
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static int priv_spec_from_str(const char *priv_spec_str)
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{
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int priv_version = -1;
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@ -2562,6 +2603,7 @@ static const Property riscv_cpu_properties[] = {
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{.name = "mmu", .info = &prop_mmu},
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{.name = "pmp", .info = &prop_pmp},
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{.name = "num-pmp-regions", .info = &prop_num_pmp_regions},
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{.name = "priv_spec", .info = &prop_priv_spec},
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{.name = "vext_spec", .info = &prop_vext_spec},
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@ -2932,7 +2974,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.max_satp_mode = VM_1_10_MBARE,
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.cfg.ext_zifencei = true,
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.cfg.ext_zicsr = true,
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.cfg.pmp = true
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.cfg.pmp = true,
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.cfg.pmp_regions = 8
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),
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DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_CPU,
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@ -2943,7 +2986,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.ext_zifencei = true,
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.cfg.ext_zicsr = true,
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.cfg.mmu = true,
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.cfg.pmp = true
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.cfg.pmp = true,
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.cfg.pmp_regions = 8
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),
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#if defined(TARGET_RISCV32) || \
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@ -174,7 +174,8 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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#define MAX_RISCV_PMPS (64)
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#define OLD_MAX_RISCV_PMPS (16)
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#if !defined(CONFIG_USER_ONLY)
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#include "pmp.h"
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@ -163,6 +163,7 @@ TYPED_FIELD(uint16_t, elen, 0)
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TYPED_FIELD(uint16_t, cbom_blocksize, 0)
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TYPED_FIELD(uint16_t, cbop_blocksize, 0)
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TYPED_FIELD(uint16_t, cboz_blocksize, 0)
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TYPED_FIELD(uint8_t, pmp_regions, 0)
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TYPED_FIELD(int8_t, max_satp_mode, -1)
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@ -738,7 +738,10 @@ static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno)
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static RISCVException pmp(CPURISCVState *env, int csrno)
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{
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if (riscv_cpu_cfg(env)->pmp) {
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if (csrno <= CSR_PMPCFG3) {
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int max_pmpcfg = (env->priv_ver >= PRIV_VERSION_1_12_0) ?
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+ CSR_PMPCFG15 : CSR_PMPCFG3;
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if (csrno <= max_pmpcfg) {
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uint32_t reg_index = csrno - CSR_PMPCFG0;
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/* TODO: RV128 restriction check */
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@ -36,8 +36,9 @@ static int pmp_post_load(void *opaque, int version_id)
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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int i;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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for (i = 0; i < pmp_regions; i++) {
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pmp_update_rule_addr(env, i);
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}
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pmp_update_rule_nums(env);
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@ -122,7 +122,9 @@ uint32_t pmp_get_num_rules(CPURISCVState *env)
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*/
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static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
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{
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if (pmp_index < MAX_RISCV_PMPS) {
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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if (pmp_index < pmp_regions) {
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return env->pmp_state.pmp[pmp_index].cfg_reg;
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}
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@ -136,7 +138,9 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
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*/
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static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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{
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if (pmp_index < MAX_RISCV_PMPS) {
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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if (pmp_index < pmp_regions) {
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if (env->pmp_state.pmp[pmp_index].cfg_reg == val) {
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/* no change */
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return false;
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@ -236,9 +240,10 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
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void pmp_update_rule_nums(CPURISCVState *env)
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{
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int i;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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env->pmp_state.num_rules = 0;
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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for (i = 0; i < pmp_regions; i++) {
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const uint8_t a_field =
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pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
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if (PMP_AMATCH_OFF != a_field) {
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@ -332,6 +337,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
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int pmp_size = 0;
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hwaddr s = 0;
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hwaddr e = 0;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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/* Short cut if no rules */
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if (0 == pmp_get_num_rules(env)) {
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@ -356,7 +362,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
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* 1.10 draft priv spec states there is an implicit order
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* from low to high
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*/
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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for (i = 0; i < pmp_regions; i++) {
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s = pmp_is_in_range(env, i, addr);
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e = pmp_is_in_range(env, i, addr + pmp_size - 1);
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@ -527,8 +533,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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{
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trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
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bool is_next_cfg_tor = false;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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if (addr_index < MAX_RISCV_PMPS) {
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if (addr_index < pmp_regions) {
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if (env->pmp_state.pmp[addr_index].addr_reg == val) {
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/* no change */
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return;
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@ -538,7 +545,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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* In TOR mode, need to check the lock bit of the next pmp
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* (if there is a next).
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*/
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if (addr_index + 1 < MAX_RISCV_PMPS) {
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if (addr_index + 1 < pmp_regions) {
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uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
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is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg);
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@ -573,8 +580,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
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{
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target_ulong val = 0;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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if (addr_index < MAX_RISCV_PMPS) {
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if (addr_index < pmp_regions) {
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val = env->pmp_state.pmp[addr_index].addr_reg;
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trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
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} else {
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@ -592,6 +600,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
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{
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int i;
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uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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/* Update PMM field only if the value is valid according to Zjpm v1.0 */
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if (riscv_cpu_cfg(env)->ext_smmpm &&
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riscv_cpu_mxl(env) == MXL_RV64 &&
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@ -603,7 +612,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
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/* RLB cannot be enabled if it's already 0 and if any regions are locked */
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if (!MSECCFG_RLB_ISSET(env)) {
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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for (i = 0; i < pmp_regions; i++) {
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if (pmp_is_locked(env, i)) {
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val &= ~MSECCFG_RLB;
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break;
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@ -659,6 +668,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
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hwaddr tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
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hwaddr tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
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int i;
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uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
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/*
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* If PMP is not supported or there are no PMP rules, the TLB page will not
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@ -669,7 +679,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
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return TARGET_PAGE_SIZE;
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}
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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for (i = 0; i < pmp_regions; i++) {
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if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) == PMP_AMATCH_OFF) {
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continue;
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}
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