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hw/riscv/virt-acpi-build: Add support for RIMT
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to communicate IOMMU information to the OS. Add support for creating this table when the IOMMU is present. The specification is frozen and available at [1]. [1] - https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/download/v0.99/rimt-spec.pdf Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250322043139.2003479-3-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Sunil V L
Alistair Francis
parent
d2a88aca76
commit
cd18dbbf9d
1 changed files with 215 additions and 0 deletions
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@ -198,6 +198,32 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
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aml_append(scope, dev);
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}
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/*
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* Add DSDT entry for the IOMMU platform device.
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* ACPI ID for IOMMU is defined in the section 6.2 of RISC-V BRS spec.
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* https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.8/riscv-brs-spec.pdf
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*/
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static void acpi_dsdt_add_iommu_sys(Aml *scope, const MemMapEntry *iommu_memmap,
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uint32_t iommu_irq)
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{
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uint32_t i;
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Aml *dev = aml_device("IMU0");
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aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0004")));
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aml_append(dev, aml_name_decl("_UID", aml_int(0)));
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Aml *crs = aml_resource_template();
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aml_append(crs, aml_memory32_fixed(iommu_memmap->base,
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iommu_memmap->size, AML_READ_WRITE));
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for (i = iommu_irq; i < iommu_irq + 4; i++) {
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aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, AML_ACTIVE_LOW,
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AML_EXCLUSIVE, &i, 1));
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}
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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}
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/*
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* Serial Port Console Redirection Table (SPCR)
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* Rev: 1.10
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@ -450,6 +476,9 @@ static void build_dsdt(GArray *table_data,
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}
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acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
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if (virt_is_iommu_sys_enabled(s)) {
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acpi_dsdt_add_iommu_sys(scope, &memmap[VIRT_IOMMU_SYS], IOMMU_SYS_IRQ);
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}
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if (socket_count == 1) {
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virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
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@ -602,6 +631,187 @@ static void build_madt(GArray *table_data,
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acpi_table_end(linker, &table);
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}
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#define ID_MAPPING_ENTRY_SIZE 20
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#define IOMMU_ENTRY_SIZE 40
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#define RISCV_INTERRUPT_WIRE_OFFSSET 40
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#define ROOT_COMPLEX_ENTRY_SIZE 20
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#define RIMT_NODE_OFFSET 48
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/*
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* ID Mapping Structure
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*/
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static void build_rimt_id_mapping(GArray *table_data, uint32_t source_id_base,
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uint32_t num_ids, uint32_t dest_id_base)
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{
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/* Source ID Base */
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build_append_int_noprefix(table_data, source_id_base, 4);
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/* Number of IDs */
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build_append_int_noprefix(table_data, num_ids, 4);
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/* Destination Device ID Base */
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build_append_int_noprefix(table_data, source_id_base, 4);
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/* Destination IOMMU Offset */
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build_append_int_noprefix(table_data, dest_id_base, 4);
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/* Flags */
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build_append_int_noprefix(table_data, 0, 4);
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}
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struct AcpiRimtIdMapping {
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uint32_t source_id_base;
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uint32_t num_ids;
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};
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typedef struct AcpiRimtIdMapping AcpiRimtIdMapping;
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/* Build the rimt ID mapping to IOMMU for a given PCI host bridge */
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static int rimt_host_bridges(Object *obj, void *opaque)
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{
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GArray *idmap_blob = opaque;
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if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
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PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
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if (bus && !pci_bus_bypass_iommu(bus)) {
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int min_bus, max_bus;
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pci_bus_range(bus, &min_bus, &max_bus);
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AcpiRimtIdMapping idmap = {
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.source_id_base = min_bus << 8,
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.num_ids = (max_bus - min_bus + 1) << 8,
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};
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g_array_append_val(idmap_blob, idmap);
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}
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}
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return 0;
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}
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static int rimt_idmap_compare(gconstpointer a, gconstpointer b)
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{
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AcpiRimtIdMapping *idmap_a = (AcpiRimtIdMapping *)a;
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AcpiRimtIdMapping *idmap_b = (AcpiRimtIdMapping *)b;
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return idmap_a->source_id_base - idmap_b->source_id_base;
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}
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/*
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* RISC-V IO Mapping Table (RIMT)
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* https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/download/v0.99/rimt-spec.pdf
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*/
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static void build_rimt(GArray *table_data, BIOSLinker *linker,
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RISCVVirtState *s)
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{
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int i, nb_nodes, rc_mapping_count;
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size_t node_size, iommu_offset = 0;
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uint32_t id = 0;
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g_autoptr(GArray) iommu_idmaps = g_array_new(false, true,
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sizeof(AcpiRimtIdMapping));
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AcpiTable table = { .sig = "RIMT", .rev = 1, .oem_id = s->oem_id,
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.oem_table_id = s->oem_table_id };
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acpi_table_begin(&table, table_data);
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object_child_foreach_recursive(object_get_root(),
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rimt_host_bridges, iommu_idmaps);
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/* Sort the ID mapping by Source ID Base*/
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g_array_sort(iommu_idmaps, rimt_idmap_compare);
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nb_nodes = 2; /* RC, IOMMU */
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rc_mapping_count = iommu_idmaps->len;
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/* Number of RIMT Nodes */
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build_append_int_noprefix(table_data, nb_nodes, 4);
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/* Offset to Array of RIMT Nodes */
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build_append_int_noprefix(table_data, RIMT_NODE_OFFSET, 4);
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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iommu_offset = table_data->len - table.table_offset;
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/* IOMMU Device Structure */
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build_append_int_noprefix(table_data, 0, 1); /* Type - IOMMU*/
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build_append_int_noprefix(table_data, 1, 1); /* Revision */
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node_size = IOMMU_ENTRY_SIZE;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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build_append_int_noprefix(table_data, id++, 2); /* ID */
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if (virt_is_iommu_sys_enabled(s)) {
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/* Hardware ID */
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build_append_int_noprefix(table_data, 'R', 1);
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build_append_int_noprefix(table_data, 'S', 1);
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build_append_int_noprefix(table_data, 'C', 1);
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build_append_int_noprefix(table_data, 'V', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '4', 1);
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/* Base Address */
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build_append_int_noprefix(table_data,
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s->memmap[VIRT_IOMMU_SYS].base, 8);
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build_append_int_noprefix(table_data, 0, 4); /* Flags */
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} else {
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/* Hardware ID */
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '1', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '0', 1);
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build_append_int_noprefix(table_data, '1', 1);
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build_append_int_noprefix(table_data, '4', 1);
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build_append_int_noprefix(table_data, 0, 8); /* Base Address */
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build_append_int_noprefix(table_data, 1, 4); /* Flags */
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}
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build_append_int_noprefix(table_data, 0, 4); /* Proximity Domain */
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build_append_int_noprefix(table_data, 0, 2); /* PCI Segment number */
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/* PCIe B/D/F */
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if (virt_is_iommu_sys_enabled(s)) {
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build_append_int_noprefix(table_data, 0, 2);
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} else {
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build_append_int_noprefix(table_data, s->pci_iommu_bdf, 2);
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}
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/* Number of interrupt wires */
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build_append_int_noprefix(table_data, 0, 2);
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/* Interrupt wire array offset */
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build_append_int_noprefix(table_data, RISCV_INTERRUPT_WIRE_OFFSSET, 2);
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/* PCIe Root Complex Node */
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build_append_int_noprefix(table_data, 1, 1); /* Type */
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build_append_int_noprefix(table_data, 1, 1); /* Revision */
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node_size = ROOT_COMPLEX_ENTRY_SIZE +
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ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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build_append_int_noprefix(table_data, id++, 2); /* ID */
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build_append_int_noprefix(table_data, 0, 4); /* Flags */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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/* PCI Segment number */
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build_append_int_noprefix(table_data, 0, 2);
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/* ID mapping array offset */
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build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 2);
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/* Number of ID mappings */
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build_append_int_noprefix(table_data, rc_mapping_count, 2);
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/* Output Reference */
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AcpiRimtIdMapping *range;
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/* ID mapping array */
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for (i = 0; i < iommu_idmaps->len; i++) {
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range = &g_array_index(iommu_idmaps, AcpiRimtIdMapping, i);
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if (virt_is_iommu_sys_enabled(s)) {
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range->source_id_base = 0;
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} else {
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range->source_id_base = s->pci_iommu_bdf + 1;
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}
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range->num_ids = 0xffff - s->pci_iommu_bdf;
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build_rimt_id_mapping(table_data, range->source_id_base,
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range->num_ids, iommu_offset);
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}
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acpi_table_end(linker, &table);
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}
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/*
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* ACPI spec, Revision 6.5+
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* 5.2.16 System Resource Affinity Table (SRAT)
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@ -679,6 +889,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
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acpi_add_table(table_offsets, tables_blob);
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build_rhct(tables_blob, tables->linker, s);
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if (virt_is_iommu_sys_enabled(s) || s->pci_iommu_bdf) {
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acpi_add_table(table_offsets, tables_blob);
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build_rimt(tables_blob, tables->linker, s);
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}
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acpi_add_table(table_offsets, tables_blob);
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spcr_setup(tables_blob, tables->linker, s);
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