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Hexagon HVX (target/hexagon) semantics generator - part 2
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
144da35776
commit
ccd9eec874
3 changed files with 360 additions and 22 deletions
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@ -119,10 +119,95 @@ def genptr_decl(f, tag, regtype, regid, regno):
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(regtype, regid, regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "V"):
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if (regid in {"dd"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" %\
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" %\
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(regtype, regid))
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if (hex_common.is_tmp_result(tag)):
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f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 2, true);\n" % \
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(regtype, regid))
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else:
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f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
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(regtype, regid))
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f.write(" 2, true);\n")
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid in {"uu", "vv", "xx"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" % \
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(regtype, regid))
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f.write(" offsetof(CPUHexagonState, %s%sV);\n" % \
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(regtype, regid))
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid in {"s", "u", "v", "w"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" % \
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(regtype, regid))
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f.write(" vreg_src_off(ctx, %s%sN);\n" % \
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(regtype, regid))
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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elif (regid in {"d", "x", "y"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" % \
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(regtype, regid))
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if (hex_common.is_tmp_result(tag)):
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f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \
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(regtype, regid))
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else:
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f.write(" ctx_future_vreg_off(ctx, %s%sN," % \
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(regtype, regid))
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f.write(" 1, true);\n");
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "x"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" % \
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(regtype, regid))
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f.write(" offsetof(CPUHexagonState,\n")
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f.write(" future_QRegs[%s%sN]);\n" % \
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(regtype, regid))
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid in {"s", "t", "u", "v"}):
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f.write(" const int %s%sN = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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f.write(" const intptr_t %s%sV_off =\n" %\
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(regtype, regid))
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f.write(" offsetof(CPUHexagonState, QRegs[%s%sN]);\n" % \
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(regtype, regid))
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
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(regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_decl_new(f,regtype,regid,regno):
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def genptr_decl_new(f, tag, regtype, regid, regno):
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if (regtype == "N"):
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if (regid in {"s", "t"}):
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f.write(" TCGv %s%sN = hex_new_value[insn->regno[%d]];\n" % \
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@ -135,6 +220,21 @@ def genptr_decl_new(f,regtype,regid,regno):
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(regtype, regid, regno))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "O"):
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if (regid == "s"):
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f.write(" const intptr_t %s%sN_num = insn->regno[%d];\n" % \
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(regtype, regid, regno))
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if (hex_common.skip_qemu_helper(tag)):
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f.write(" const intptr_t %s%sN_off =\n" % \
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(regtype, regid))
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f.write(" ctx_future_vreg_off(ctx, %s%sN_num," % \
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(regtype, regid))
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f.write(" 1, true);\n")
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else:
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f.write(" TCGv %s%sN = tcg_constant_tl(%s%sN_num);\n" % \
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(regtype, regid, regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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@ -145,7 +245,7 @@ def genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i):
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if hex_common.is_old_val(regtype, regid, tag):
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genptr_decl(f,tag, regtype, regid, i)
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elif hex_common.is_new_val(regtype, regid, tag):
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genptr_decl_new(f,regtype,regid,i)
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genptr_decl_new(f, tag, regtype, regid, i)
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else:
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print("Bad register parse: ",regtype,regid,toss,numregs)
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else:
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@ -159,7 +259,7 @@ def genptr_decl_imm(f,immlett):
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f.write(" int %s = insn->immed[%d];\n" % \
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(hex_common.imm_name(immlett), i))
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def genptr_free(f,regtype,regid,regno):
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def genptr_free(f, tag, regtype, regid, regno):
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if (regtype == "R"):
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if (regid in {"dd", "ss", "tt", "xx", "yy"}):
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f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid))
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@ -182,33 +282,51 @@ def genptr_free(f,regtype,regid,regno):
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elif (regtype == "M"):
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if (regid != "u"):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "V"):
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if (regid in {"dd", "uu", "vv", "xx", \
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"d", "s", "u", "v", "w", "x", "y"}):
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
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(regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "s", "t", "u", "v", "x"}):
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
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(regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_free_new(f,regtype,regid,regno):
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def genptr_free_new(f, tag, regtype, regid, regno):
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if (regtype == "N"):
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if (regid not in {"s", "t"}):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "P"):
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if (regid not in {"t", "u", "v"}):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "O"):
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if (regid != "s"):
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_free_opn(f,regtype,regid,i,tag):
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if (hex_common.is_pair(regid)):
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genptr_free(f,regtype,regid,i)
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genptr_free(f, tag, regtype, regid, i)
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elif (hex_common.is_single(regid)):
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if hex_common.is_old_val(regtype, regid, tag):
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genptr_free(f,regtype,regid,i)
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genptr_free(f, tag, regtype, regid, i)
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elif hex_common.is_new_val(regtype, regid, tag):
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genptr_free_new(f,regtype,regid,i)
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genptr_free_new(f, tag, regtype, regid, i)
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else:
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print("Bad register parse: ",regtype,regid,toss,numregs)
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else:
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print("Bad register parse: ",regtype,regid,toss,numregs)
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def genptr_src_read(f,regtype,regid):
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def genptr_src_read(f, tag, regtype, regid):
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if (regtype == "R"):
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if (regid in {"ss", "tt", "xx", "yy"}):
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f.write(" tcg_gen_concat_i32_i64(%s%sV, hex_gpr[%s%sN],\n" % \
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@ -238,6 +356,47 @@ def genptr_src_read(f,regtype,regid):
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elif (regtype == "M"):
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if (regid != "u"):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "V"):
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if (regid in {"uu", "vv", "xx"}):
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f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
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(regtype, regid))
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f.write(" vreg_src_off(ctx, %s%sN),\n" % \
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(regtype, regid))
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f.write(" sizeof(MMVector), sizeof(MMVector));\n")
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f.write(" tcg_gen_gvec_mov(MO_64,\n")
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f.write(" %s%sV_off + sizeof(MMVector),\n" % \
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(regtype, regid))
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f.write(" vreg_src_off(ctx, %s%sN ^ 1),\n" % \
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(regtype, regid))
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f.write(" sizeof(MMVector), sizeof(MMVector));\n")
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elif (regid in {"s", "u", "v", "w"}):
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid in {"x", "y"}):
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f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
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(regtype, regid))
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f.write(" vreg_src_off(ctx, %s%sN),\n" % \
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(regtype, regid))
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f.write(" sizeof(MMVector), sizeof(MMVector));\n")
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"s", "t", "u", "v"}):
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if (not hex_common.skip_qemu_helper(tag)):
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f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid in {"x"}):
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f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
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(regtype, regid))
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f.write(" offsetof(CPUHexagonState, QRegs[%s%sN]),\n" % \
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(regtype, regid))
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f.write(" sizeof(MMQReg), sizeof(MMQReg));\n")
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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@ -248,15 +407,18 @@ def genptr_src_read_new(f,regtype,regid):
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elif (regtype == "P"):
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if (regid not in {"t", "u", "v"}):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "O"):
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if (regid != "s"):
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_src_read_opn(f,regtype,regid,tag):
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if (hex_common.is_pair(regid)):
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genptr_src_read(f,regtype,regid)
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genptr_src_read(f, tag, regtype, regid)
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elif (hex_common.is_single(regid)):
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if hex_common.is_old_val(regtype, regid, tag):
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genptr_src_read(f,regtype,regid)
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genptr_src_read(f, tag, regtype, regid)
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elif hex_common.is_new_val(regtype, regid, tag):
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genptr_src_read_new(f,regtype,regid)
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else:
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@ -331,11 +493,68 @@ def genptr_dst_write(f, tag, regtype, regid):
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
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if (regtype == "V"):
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if (regid in {"dd", "xx", "yy"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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f.write(" gen_log_vreg_write_pair(ctx, %s%sV_off, %s%sN, " % \
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(regtype, regid, regtype, regid))
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f.write("%s, insn->slot, %s);\n" % \
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(newv, is_predicated))
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f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \
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(regtype, regid, newv))
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f.write(" %s);\n" % (is_predicated))
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elif (regid in {"d", "x", "y"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s, " % \
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % \
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(is_predicated))
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f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \
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(regtype, regid, newv, is_predicated))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "x"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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is_predicated = "true"
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else:
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is_predicated = "false"
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f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \
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(regtype, regid, regtype, regid, newv))
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f.write("insn->slot, %s);\n" % (is_predicated))
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f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \
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(regtype, regid, is_predicated))
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_dst_write_opn(f,regtype, regid, tag):
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if (hex_common.is_pair(regid)):
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genptr_dst_write(f, tag, regtype, regid)
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if (hex_common.is_hvx_reg(regtype)):
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if (hex_common.is_tmp_result(tag)):
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genptr_dst_write_ext(f, tag, regtype, regid, "EXT_TMP")
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else:
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genptr_dst_write_ext(f, tag, regtype, regid)
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else:
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genptr_dst_write(f, tag, regtype, regid)
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elif (hex_common.is_single(regid)):
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genptr_dst_write(f, tag, regtype, regid)
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if (hex_common.is_hvx_reg(regtype)):
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if (hex_common.is_new_result(tag)):
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genptr_dst_write_ext(f, tag, regtype, regid, "EXT_NEW")
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if (hex_common.is_tmp_result(tag)):
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genptr_dst_write_ext(f, tag, regtype, regid, "EXT_TMP")
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else:
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genptr_dst_write_ext(f, tag, regtype, regid, "EXT_DFL")
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else:
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genptr_dst_write(f, tag, regtype, regid)
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else:
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print("Bad register parse: ",regtype,regid,toss,numregs)
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@ -406,13 +625,24 @@ def gen_tcg_func(f, tag, regs, imms):
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## If there is a scalar result, it is the return type
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_written(regid)):
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if (hex_common.is_hvx_reg(regtype)):
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continue
|
||||
gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
|
||||
i += 1
|
||||
if (i > 0): f.write(", ")
|
||||
f.write("cpu_env")
|
||||
i=1
|
||||
for regtype,regid,toss,numregs in regs:
|
||||
if (hex_common.is_written(regid)):
|
||||
if (not hex_common.is_hvx_reg(regtype)):
|
||||
continue
|
||||
gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
|
||||
i += 1
|
||||
for regtype,regid,toss,numregs in regs:
|
||||
if (hex_common.is_read(regid)):
|
||||
if (hex_common.is_hvx_reg(regtype) and
|
||||
hex_common.is_readwrite(regid)):
|
||||
continue
|
||||
gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
|
||||
i += 1
|
||||
for immlett,bits,immshift in imms:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue