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target/arm: Make dummy debug registers RAZ, not NOP

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In debug_helper.c we provide a few dummy versions of
debug registers:
 * DBGVCR (AArch32 only): enable bits for vector-catch
   debug events
 * MDCCINT_EL1: interrupt enable bits for the DCC
   debug communications channel
 * DBGVCR32_EL2: the AArch64 accessor for the state in
   DBGVCR

We implemented these only to stop Linux crashing on startup,
but we chose to implement them as ARM_CP_NOP. This worked
for Linux where it only cares about trying to write to these
registers, but is very confusing behaviour for anything that
wants to read the registers (perhaps for context state switches),
because the destination register will be left with whatever
random value it happened to have before the read.

Model these registers instead as RAZ.

Fixes: 5e8b12ffbb ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0")
Fixes: 5dbdc4342f ("target-arm: Implement dummy MDCCINT_EL1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2025-02-28 16:24:24 +00:00
parent 5be4419c57
commit cc503abf4b
1 changed files with 4 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/arm/debug_helper.c
View file

@ -1037,7 +1037,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
{ .name = "DBGVCR", { .name = "DBGVCR",
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda, .access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP }, .type = ARM_CP_CONST, .resetvalue = 0 },
/* /*
* Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Dummy MDCCINT_EL1, since we don't implement the Debug Communications
* Channel but Linux may try to access this register. The 32-bit * Channel but Linux may try to access this register. The 32-bit
@ -1046,7 +1046,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tdcc, .access = PL1_RW, .accessfn = access_tdcc,
.type = ARM_CP_NOP }, .type = ARM_CP_CONST, .resetvalue = 0 },
/* /*
* Dummy DBGCLAIM registers. * Dummy DBGCLAIM registers.
* "The architecture does not define any functionality for the CLAIM tag bits.", * "The architecture does not define any functionality for the CLAIM tag bits.",
@ -1075,7 +1075,8 @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = {
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL2_RW, .accessfn = access_dbgvcr32, .access = PL2_RW, .accessfn = access_dbgvcr32,
.type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP,
.resetvalue = 0 },
}; };
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {