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Add nuvoton sd module for NPCM7XX
Add gdb-xml for MVE More uses of tcg_constant_* in target/arm Fix parameter naming for default-bus-bypass-iommu Ignore cache operations to mmio in HVF -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmGBgjkdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8sAAgAsHaW2sHH/W4TzCwl DfqFar4u047Q+ZtQHjNehGHF9Bxp4NS4A0qL52vk0hVoqeWlyF1N29MOnewgVDqY q1x+uxJtG9xjTse7oEEshEEFF/7J8eB8dN4E78TFn/6IhvVhGiUeeRu29s44Ot6N E2KABcXfd+4gEdqhepLGEbi5n0TnA8ARmmeffZNWVEbsxQjHnMQQYmqGmllB3xV3 qPpnp3avvD1015zMwrLVmlDO+tSRr/1bed7k3k26ebga2B/zitxcpXFNCDlgePx0 LNT5QYvBDpE7HOruGQjf4iXPJHfYw5VMtopK7K++rY9KWiJgBVSjQUcB462sdCPk wNAp0g== =vlZ5 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211102-2' into staging Add nuvoton sd module for NPCM7XX Add gdb-xml for MVE More uses of tcg_constant_* in target/arm Fix parameter naming for default-bus-bypass-iommu Ignore cache operations to mmio in HVF # gpg: Signature made Tue 02 Nov 2021 02:23:53 PM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-arm-20211102-2: hvf: arm: Ignore cache operations on MMIO hw/arm/virt: Rename default_bus_bypass_iommu target/arm: Use tcg_constant_i32() in gen_rev16() target/arm: Use tcg_constant_i64() in do_sat_addsub_64() target/arm: Use the constant variant of store_cpu_field() when possible target/arm: Introduce store_cpu_field_constant() helper target/arm: Use tcg_constant_i32() in op_smlad() target/arm: Advertise MVE to gdb when present tests/qtest/libqos: add SDHCI commands hw/arm: Attach MMC to quanta-gbs-bmc hw/arm: Add Nuvoton SD module to board hw/sd: add nuvoton MMC Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
cc23377516
20 changed files with 544 additions and 35 deletions
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@ -5,6 +5,7 @@ libqos_srcs = files('../libqtest.c',
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'fw_cfg.c',
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'malloc.c',
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'libqos.c',
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'sdhci-cmd.c',
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# spapr
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'malloc-spapr.c',
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116
tests/qtest/libqos/sdhci-cmd.c
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116
tests/qtest/libqos/sdhci-cmd.c
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@ -0,0 +1,116 @@
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/*
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* MMC Host Controller Commands
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*
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* Copyright (c) 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "sdhci-cmd.h"
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#include "libqtest.h"
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static ssize_t read_fifo(QTestState *qts, uint64_t reg, char *msg, size_t count)
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{
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uint32_t mask = 0xff;
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size_t index = 0;
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uint32_t msg_frag;
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int size;
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while (index < count) {
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size = count - index;
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if (size > 4) {
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size = 4;
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}
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msg_frag = qtest_readl(qts, reg);
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while (size > 0) {
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msg[index] = msg_frag & mask;
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if (msg[index++] == 0) {
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return index;
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}
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msg_frag >>= 8;
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--size;
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}
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}
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return index;
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}
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static void write_fifo(QTestState *qts, uint64_t reg, const char *msg,
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size_t count)
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{
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size_t index = 0;
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uint32_t msg_frag;
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int size;
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int frag_i;
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while (index < count) {
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size = count - index;
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if (size > 4) {
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size = 4;
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}
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msg_frag = 0;
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frag_i = 0;
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while (frag_i < size) {
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msg_frag |= ((uint32_t)msg[index++]) << (frag_i * 8);
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++frag_i;
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}
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qtest_writel(qts, reg, msg_frag);
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}
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}
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static void fill_block(QTestState *qts, uint64_t reg, int count)
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{
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while (--count >= 0) {
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qtest_writel(qts, reg, 0);
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}
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}
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void sdhci_cmd_regs(QTestState *qts, uint64_t base_addr, uint16_t blksize,
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uint16_t blkcnt, uint32_t argument, uint16_t trnmod,
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uint16_t cmdreg)
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{
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qtest_writew(qts, base_addr + SDHC_BLKSIZE, blksize);
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qtest_writew(qts, base_addr + SDHC_BLKCNT, blkcnt);
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qtest_writel(qts, base_addr + SDHC_ARGUMENT, argument);
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qtest_writew(qts, base_addr + SDHC_TRNMOD, trnmod);
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qtest_writew(qts, base_addr + SDHC_CMDREG, cmdreg);
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}
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ssize_t sdhci_read_cmd(QTestState *qts, uint64_t base_addr, char *msg,
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size_t count)
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{
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sdhci_cmd_regs(qts, base_addr, count, 1, 0,
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SDHC_TRNS_MULTI | SDHC_TRNS_READ | SDHC_TRNS_BLK_CNT_EN,
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SDHC_READ_MULTIPLE_BLOCK | SDHC_CMD_DATA_PRESENT);
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/* read sd fifo_buffer */
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ssize_t bytes_read = read_fifo(qts, base_addr + SDHC_BDATA, msg, count);
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sdhci_cmd_regs(qts, base_addr, 0, 0, 0,
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SDHC_TRNS_MULTI | SDHC_TRNS_READ | SDHC_TRNS_BLK_CNT_EN,
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SDHC_STOP_TRANSMISSION);
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return bytes_read;
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}
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void sdhci_write_cmd(QTestState *qts, uint64_t base_addr, const char *msg,
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size_t count, size_t blksize)
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{
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sdhci_cmd_regs(qts, base_addr, blksize, 1, 0,
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SDHC_TRNS_MULTI | SDHC_TRNS_WRITE | SDHC_TRNS_BLK_CNT_EN,
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SDHC_WRITE_MULTIPLE_BLOCK | SDHC_CMD_DATA_PRESENT);
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/* write to sd fifo_buffer */
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write_fifo(qts, base_addr + SDHC_BDATA, msg, count);
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fill_block(qts, base_addr + SDHC_BDATA, (blksize - count) / 4);
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sdhci_cmd_regs(qts, base_addr, 0, 0, 0,
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SDHC_TRNS_MULTI | SDHC_TRNS_WRITE | SDHC_TRNS_BLK_CNT_EN,
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SDHC_STOP_TRANSMISSION);
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}
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70
tests/qtest/libqos/sdhci-cmd.h
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70
tests/qtest/libqos/sdhci-cmd.h
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@ -0,0 +1,70 @@
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/*
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* MMC Host Controller Commands
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*
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* Copyright (c) 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "libqtest.h"
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/* more details at hw/sd/sdhci-internal.h */
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#define SDHC_BLKSIZE 0x04
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#define SDHC_BLKCNT 0x06
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#define SDHC_ARGUMENT 0x08
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#define SDHC_TRNMOD 0x0C
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#define SDHC_CMDREG 0x0E
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#define SDHC_BDATA 0x20
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#define SDHC_PRNSTS 0x24
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#define SDHC_BLKGAP 0x2A
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#define SDHC_CLKCON 0x2C
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#define SDHC_SWRST 0x2F
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#define SDHC_CAPAB 0x40
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#define SDHC_MAXCURR 0x48
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#define SDHC_HCVER 0xFE
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/* TRNSMOD Reg */
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#define SDHC_TRNS_BLK_CNT_EN 0x0002
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#define SDHC_TRNS_READ 0x0010
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#define SDHC_TRNS_WRITE 0x0000
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#define SDHC_TRNS_MULTI 0x0020
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/* CMD Reg */
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#define SDHC_CMD_DATA_PRESENT (1 << 5)
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#define SDHC_ALL_SEND_CID (2 << 8)
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#define SDHC_SEND_RELATIVE_ADDR (3 << 8)
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#define SDHC_SELECT_DESELECT_CARD (7 << 8)
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#define SDHC_SEND_CSD (9 << 8)
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#define SDHC_STOP_TRANSMISSION (12 << 8)
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#define SDHC_READ_MULTIPLE_BLOCK (18 << 8)
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#define SDHC_WRITE_MULTIPLE_BLOCK (25 << 8)
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#define SDHC_APP_CMD (55 << 8)
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/* SWRST Reg */
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#define SDHC_RESET_ALL 0x01
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/* CLKCTRL Reg */
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#define SDHC_CLOCK_INT_EN 0x0001
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#define SDHC_CLOCK_INT_STABLE 0x0002
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#define SDHC_CLOCK_SDCLK_EN (1 << 2)
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/* Set registers needed to send commands to SD */
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void sdhci_cmd_regs(QTestState *qts, uint64_t base_addr, uint16_t blksize,
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uint16_t blkcnt, uint32_t argument, uint16_t trnmod,
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uint16_t cmdreg);
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/* Read at most 1 block of SD using non-DMA */
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ssize_t sdhci_read_cmd(QTestState *qts, uint64_t base_addr, char *msg,
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size_t count);
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/* Write at most 1 block of SD using non-DMA */
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void sdhci_write_cmd(QTestState *qts, uint64_t base_addr, const char *msg,
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size_t count, size_t blksize);
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