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cpu: move cc->transaction_failed to tcg_ops

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Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]

avoiding its use in headers used by common_ss code (should be poisoned).

Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Claudio Fontana 2021-02-04 17:39:18 +01:00 • committed by Richard Henderson
parent 0545608056
commit cbc183d2d9
12 changed files with 34 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/alpha/cpu.c
View file

@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;

4
target/arm/cpu.c
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@ -2283,11 +2283,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
#endif /* CONFIG_TCG */
}
#ifdef CONFIG_KVM

2
target/m68k/cpu.c
View file

@ -473,7 +473,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
cc->do_transaction_failed = m68k_cpu_transaction_failed;
cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
#endif

2
target/microblaze/cpu.c
View file

@ -374,7 +374,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mb_cpu_transaction_failed;
cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif

4
target/mips/cpu.c
View file

@ -681,7 +681,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
@ -693,6 +692,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;

2
target/riscv/cpu.c
View file

@ -609,7 +609,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */

2
target/riscv/cpu_helper.c
View file

@ -671,7 +671,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#endif
#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,

2
target/sparc/cpu.c
View file

@ -875,7 +875,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;

2
target/xtensa/cpu.c
View file

@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;

4
target/xtensa/helper.c
View file

@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
#else
#else /* !CONFIG_USER_ONLY */
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
qemu_cpu_kick(cpu);
}
}
#endif
#endif /* !CONFIG_USER_ONLY */