motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-09 02:24:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs

Browse source 
As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
let's rename 32bit ones to avoid confusion.

This is a mechanical patch so it does not fix obvious mistake with these
registers in POWER7 yet, this will be fixed later.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexey Kardashevskiy 2014-06-04 22:50:36 +10:00 • committed by Alexander Graf
parent a9e8f4e7df
commit cb8b8bf840
2 changed files with 69 additions and 69 deletions
Download patch file Download diff file Expand all files Collapse all files

40
target-ppc/cpu.h
View file

@ -1562,24 +1562,24 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_DCDBTRH (0x39D)
#define SPR_BOOKE_ICDBTRL (0x39E)
#define SPR_BOOKE_ICDBTRH (0x39F)
#define SPR_UMMCR2 (0x3A0)
#define SPR_UPMC5 (0x3A1)
#define SPR_UPMC6 (0x3A2)
#define SPR_74XX_UMMCR2 (0x3A0)
#define SPR_7XX_UPMC5 (0x3A1)
#define SPR_7XX_UPMC6 (0x3A2)
#define SPR_UBAMR (0x3A7)
#define SPR_UMMCR0 (0x3A8)
#define SPR_UPMC1 (0x3A9)
#define SPR_UPMC2 (0x3AA)
#define SPR_USIAR (0x3AB)
#define SPR_UMMCR1 (0x3AC)
#define SPR_UPMC3 (0x3AD)
#define SPR_UPMC4 (0x3AE)
#define SPR_7XX_UMMCR0 (0x3A8)
#define SPR_7XX_UPMC1 (0x3A9)
#define SPR_7XX_UPMC2 (0x3AA)
#define SPR_7XX_USIAR (0x3AB)
#define SPR_7XX_UMMCR1 (0x3AC)
#define SPR_7XX_UPMC3 (0x3AD)
#define SPR_7XX_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
#define SPR_40x_ZPR (0x3B0)
#define SPR_BOOKE_MAS7 (0x3B0)
#define SPR_MMCR2 (0x3B0)
#define SPR_PMC5 (0x3B1)
#define SPR_74XX_MMCR2 (0x3B0)
#define SPR_7XX_PMC5 (0x3B1)
#define SPR_40x_PID (0x3B1)
#define SPR_PMC6 (0x3B2)
#define SPR_7XX_PMC6 (0x3B2)
#define SPR_440_MMUCR (0x3B2)
#define SPR_4xx_CCR0 (0x3B3)
#define SPR_BOOKE_EPLC (0x3B3)
@ -1589,19 +1589,19 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_405_DVC1 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
#define SPR_BAMR (0x3B7)
#define SPR_MMCR0 (0x3B8)
#define SPR_PMC1 (0x3B9)
#define SPR_7XX_MMCR0 (0x3B8)
#define SPR_7XX_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
#define SPR_PMC2 (0x3BA)
#define SPR_7XX_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
#define SPR_SIAR (0x3BB)
#define SPR_7XX_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
#define SPR_MMCR1 (0x3BC)
#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
#define SPR_PMC3 (0x3BD)
#define SPR_7XX_PMC3 (0x3BD)
#define SPR_405_DBCR1 (0x3BD)
#define SPR_PMC4 (0x3BE)
#define SPR_7XX_PMC4 (0x3BE)
#define SPR_SDA (0x3BF)
#define SPR_403_VTBL (0x3CC)
#define SPR_403_VTBU (0x3CD)