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target/arm: Implement bfloat16 dot product (vector)

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This is BFDOT for both AArch64 AdvSIMD and SVE,
and VDOT.BF16 for AArch32 NEON.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-25 15:58:11 -07:00 • committed by Peter Maydell
parent 60c8f7265d
commit cb8657f7f9
7 changed files with 89 additions and 0 deletions
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20
target/arm/translate-a64.c
View file

@ -12235,6 +12235,16 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = dc_isar_feature(aa64_fcma, s);
break;
case 0x1f: /* BFDOT */
switch (size) {
case 1:
feature = dc_isar_feature(aa64_bf16, s);
break;
default:
unallocated_encoding(s);
return;
}
break;
default:
unallocated_encoding(s);
return;
@ -12318,6 +12328,16 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
return;
case 0xf: /* BFDOT */
switch (size) {
case 1:
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfdot);
break;
default:
g_assert_not_reached();
}
return;
default:
g_assert_not_reached();
}