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i.MX: Split the CCM class into an abstract base class and a concrete class

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The IMX_CCM class is now the base abstract class that is used by EPIT
and GPT timer implementation.

IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC.

For now the i.MX25 continues to use the i.MX31 CCM implementation.

An i.MX25 specific CCM will be introduced in a later patch.

We also rework initialization to stop using deprecated sysbus device init.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois 2015-12-17 13:37:15 +00:00 • committed by Peter Maydell
parent aaa9ec3b4d
commit cb54d868c6
11 changed files with 521 additions and 268 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/misc/Makefile.objs
View file

@ -26,6 +26,7 @@ obj-$(CONFIG_NSERIES) += cbus.o
obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o
obj-$(CONFIG_IMX) += imx_ccm.o
obj-$(CONFIG_IMX) += imx31_ccm.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o

392
hw/misc/imx31_ccm.c Normal file
View file

@ -0,0 +1,392 @@
/*
* IMX31 Clock Control Module
*
* Copyright (C) 2012 NICTA
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* To get the timer frequencies right, we need to emulate at least part of
* the i.MX31 CCM.
*/
#include "hw/misc/imx31_ccm.h"
#define CKIH_FREQ 26000000 /* 26MHz crystal input */
#ifndef DEBUG_IMX31_CCM
#define DEBUG_IMX31_CCM 0
#endif
#define DPRINTF(fmt, args...) \
do { \
if (DEBUG_IMX31_CCM) { \
fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
__func__, ##args); \
} \
} while (0)
static char const *imx31_ccm_reg_name(uint32_t reg)
{
switch (reg) {
case 0:
return "CCMR";
case 1:
return "PDR0";
case 2:
return "PDR1";
case 3:
return "RCSR";
case 4:
return "MPCTL";
case 5:
return "UPCTL";
case 6:
return "SPCTL";
case 7:
return "COSR";
case 8:
return "CGR0";
case 9:
return "CGR1";
case 10:
return "CGR2";
case 11:
return "WIMR";
case 12:
return "LDC";
case 13:
return "DCVR0";
case 14:
return "DCVR1";
case 15:
return "DCVR2";
case 16:
return "DCVR3";
case 17:
return "LTR0";
case 18:
return "LTR1";
case 19:
return "LTR2";
case 20:
return "LTR3";
case 21:
return "LTBR0";
case 22:
return "LTBR1";
case 23:
return "PMCR0";
case 24:
return "PMCR1";
case 25:
return "PDR2";
default:
return "???";
}
}
static const VMStateDescription vmstate_imx31_ccm = {
.name = TYPE_IMX31_CCM,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ccmr, IMX31CCMState),
VMSTATE_UINT32(pdr0, IMX31CCMState),
VMSTATE_UINT32(pdr1, IMX31CCMState),
VMSTATE_UINT32(mpctl, IMX31CCMState),
VMSTATE_UINT32(spctl, IMX31CCMState),
VMSTATE_UINT32_ARRAY(cgr, IMX31CCMState, 3),
VMSTATE_UINT32(pmcr0, IMX31CCMState),
VMSTATE_UINT32(pmcr1, IMX31CCMState),
VMSTATE_END_OF_LIST()
},
};
static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
{
uint32_t freq = 0;
IMX31CCMState *s = IMX31_CCM(dev);
if ((s->ccmr & CCMR_PRCS) == 2) {
if (s->ccmr & CCMR_FPME) {
freq = CKIL_FREQ;
if (s->ccmr & CCMR_FPMF) {
freq *= 1024;
}
}
} else {
freq = CKIH_FREQ;
}
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
freq = imx_ccm_calc_pll(s->mpctl, imx31_ccm_get_pll_ref_clk(dev));
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
if ((s->ccmr & CCMR_MDS) || !(s->ccmr & CCMR_MPE)) {
freq = imx31_ccm_get_pll_ref_clk(dev);
} else {
freq = imx31_ccm_get_mpll_clk(dev);
}
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, MCU));
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, HSP));
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, MAX));
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
{
uint32_t freq;
IMX31CCMState *s = IMX31_CCM(dev);
freq = imx31_ccm_get_hclk_clk(dev) / (1 + EXTRACT(s->pdr0, IPG));
DPRINTF("freq = %d\n", freq);
return freq;
}
static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
uint32_t freq = 0;
switch (clock) {
case NOCLK:
break;
case CLK_MCU:
freq = imx31_ccm_get_mcu_clk(dev);
break;
case CLK_HSP:
freq = imx31_ccm_get_hsp_clk(dev);
break;
case CLK_IPG:
freq = imx31_ccm_get_ipg_clk(dev);
break;
case CLK_32k:
freq = CKIL_FREQ;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
TYPE_IMX31_CCM, __func__, clock);
break;
}
DPRINTF("Clock = %d) = %d\n", clock, freq);
return freq;
}
static void imx31_ccm_reset(DeviceState *dev)
{
IMX31CCMState *s = IMX31_CCM(dev);
DPRINTF("()\n");
s->ccmr = 0x074b0b7d;
s->pdr0 = 0xff870b48;
s->pdr1 = 0x49fcfe7f;
s->mpctl = 0x04001800;
s->cgr[0] = s->cgr[1] = s->cgr[2] = 0xffffffff;
s->spctl = 0x04043001;
s->pmcr0 = 0x80209828;
s->pmcr1 = 0x00aa0000;
}
static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
{
uint32 value = 0;
IMX31CCMState *s = (IMX31CCMState *)opaque;
switch (offset >> 2) {
case 0: /* CCMR */
value = s->ccmr;
break;
case 1:
value = s->pdr0;
break;
case 2:
value = s->pdr1;
break;
case 4:
value = s->mpctl;
break;
case 6:
value = s->spctl;
break;
case 8:
value = s->cgr[0];
break;
case 9:
value = s->cgr[1];
break;
case 10:
value = s->cgr[2];
break;
case 18: /* LTR1 */
value = 0x00004040;
break;
case 23:
value = s->pmcr0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
break;
}
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
value);
return (uint64_t)value;
}
static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMX31CCMState *s = (IMX31CCMState *)opaque;
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
(uint32_t)value);
switch (offset >> 2) {
case 0:
s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
break;
case 1:
s->pdr0 = value & 0xff9f3fff;
break;
case 2:
s->pdr1 = value;
break;
case 4:
s->mpctl = value & 0xbfff3fff;
break;
case 6:
s->spctl = value & 0xbfff3fff;
break;
case 8:
s->cgr[0] = value;
break;
case 9:
s->cgr[1] = value;
break;
case 10:
s->cgr[2] = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
break;
}
}
static const struct MemoryRegionOps imx31_ccm_ops = {
.read = imx31_ccm_read,
.write = imx31_ccm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
/*
* Our device would not work correctly if the guest was doing
* unaligned access. This might not be a limitation on the real
* device but in practice there is no reason for a guest to access
* this device unaligned.
*/
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void imx31_ccm_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
IMX31CCMState *s = IMX31_CCM(obj);
memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
TYPE_IMX31_CCM, 0x1000);
sysbus_init_mmio(sd, &s->iomem);
}
static void imx31_ccm_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
dc->reset = imx31_ccm_reset;
dc->vmsd = &vmstate_imx31_ccm;
dc->desc = "i.MX31 Clock Control Module";
ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
}
static const TypeInfo imx31_ccm_info = {
.name = TYPE_IMX31_CCM,
.parent = TYPE_IMX_CCM,
.instance_size = sizeof(IMX31CCMState),
.instance_init = imx31_ccm_init,
.class_init = imx31_ccm_class_init,
};
static void imx31_ccm_register_types(void)
{
type_register_static(&imx31_ccm_info);
}
type_init(imx31_ccm_register_types)

231
hw/misc/imx_ccm.c
View file

@ -7,15 +7,12 @@
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* To get the timer frequencies right, we need to emulate at least part of
* the CCM.
* This is an abstract base class used to get a common interface to
* retrieve the CCM frequencies from the various i.MX SOC.
*/
#include "hw/misc/imx_ccm.h"
#define CKIH_FREQ 26000000 /* 26MHz crystal input */
#define CKIL_FREQ 32768 /* nominal 32khz clock */
#ifndef DEBUG_IMX_CCM
#define DEBUG_IMX_CCM 0
#endif
@ -28,51 +25,27 @@
} \
} while (0)
static int imx_ccm_post_load(void *opaque, int version_id);
static const VMStateDescription vmstate_imx_ccm = {
.name = TYPE_IMX_CCM,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ccmr, IMXCCMState),
VMSTATE_UINT32(pdr0, IMXCCMState),
VMSTATE_UINT32(pdr1, IMXCCMState),
VMSTATE_UINT32(mpctl, IMXCCMState),
VMSTATE_UINT32(spctl, IMXCCMState),
VMSTATE_UINT32_ARRAY(cgr, IMXCCMState, 3),
VMSTATE_UINT32(pmcr0, IMXCCMState),
VMSTATE_UINT32(pmcr1, IMXCCMState),
VMSTATE_UINT32(pll_refclk_freq, IMXCCMState),
VMSTATE_END_OF_LIST()
},
.post_load = imx_ccm_post_load,
};
uint32_t imx_ccm_get_clock_frequency(DeviceState *dev, IMXClk clock)
uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
IMXCCMState *s = IMX_CCM(dev);
uint32_t freq = 0;
IMXCCMClass *klass = IMX_GET_CLASS(dev);
switch (clock) {
case NOCLK:
return 0;
case CLK_MCU:
return s->mcu_clk_freq;
case CLK_HSP:
return s->hsp_clk_freq;
case CLK_IPG:
return s->ipg_clk_freq;
case CLK_32k:
return CKIL_FREQ;
if (klass->get_clock_frequency) {
freq = klass->get_clock_frequency(dev, clock);
}
return 0;
DPRINTF("(clock = %d) = %d\n", clock, freq);
return freq;
}
/*
* Calculate PLL output frequency
*/
static uint32_t calc_pll(uint32_t pllreg, uint32_t base_freq)
uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq)
{
int32_t freq;
int32_t mfn = MFN(pllreg); /* Numerator */
uint32_t mfi = MFI(pllreg); /* Integer part */
uint32_t mfd = 1 + MFD(pllreg); /* Denominator */
@ -81,186 +54,26 @@ static uint32_t calc_pll(uint32_t pllreg, uint32_t base_freq)
if (mfi < 5) {
mfi = 5;
}
/* mfn is 10-bit signed twos-complement */
mfn <<= 32 - 10;
mfn >>= 32 - 10;
return ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
(mfd * pd)) << 10;
}
static void update_clocks(IMXCCMState *s)
{
/*
* If we ever emulate more clocks, this should switch to a data-driven
* approach
*/
DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq,
freq);
if ((s->ccmr & CCMR_PRCS) == 2) {
s->pll_refclk_freq = CKIL_FREQ * 1024;
} else {
s->pll_refclk_freq = CKIH_FREQ;
}
/* ipg_clk_arm aka MCU clock */
if ((s->ccmr & CCMR_MDS) || !(s->ccmr & CCMR_MPE)) {
s->mcu_clk_freq = s->pll_refclk_freq;
} else {
s->mcu_clk_freq = calc_pll(s->mpctl, s->pll_refclk_freq);
}
/* High-speed clock */
s->hsp_clk_freq = s->mcu_clk_freq / (1 + EXTRACT(s->pdr0, HSP));
s->ipg_clk_freq = s->hsp_clk_freq / (1 + EXTRACT(s->pdr0, IPG));
DPRINTF("mcu %uMHz, HSP %uMHz, IPG %uHz\n",
s->mcu_clk_freq / 1000000,
s->hsp_clk_freq / 1000000,
s->ipg_clk_freq);
}
static void imx_ccm_reset(DeviceState *dev)
{
IMXCCMState *s = IMX_CCM(dev);
s->ccmr = 0x074b0b7d;
s->pdr0 = 0xff870b48;
s->pdr1 = 0x49fcfe7f;
s->mpctl = PLL_PD(1) | PLL_MFD(0) | PLL_MFI(6) | PLL_MFN(0);
s->cgr[0] = s->cgr[1] = s->cgr[2] = 0xffffffff;
s->spctl = PLL_PD(1) | PLL_MFD(4) | PLL_MFI(0xc) | PLL_MFN(1);
s->pmcr0 = 0x80209828;
update_clocks(s);
}
static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
DPRINTF("(offset=0x%" HWADDR_PRIx ")\n", offset);
switch (offset >> 2) {
case 0: /* CCMR */
DPRINTF(" ccmr = 0x%x\n", s->ccmr);
return s->ccmr;
case 1:
DPRINTF(" pdr0 = 0x%x\n", s->pdr0);
return s->pdr0;
case 2:
DPRINTF(" pdr1 = 0x%x\n", s->pdr1);
return s->pdr1;
case 4:
DPRINTF(" mpctl = 0x%x\n", s->mpctl);
return s->mpctl;
case 6:
DPRINTF(" spctl = 0x%x\n", s->spctl);
return s->spctl;
case 8:
DPRINTF(" cgr0 = 0x%x\n", s->cgr[0]);
return s->cgr[0];
case 9:
DPRINTF(" cgr1 = 0x%x\n", s->cgr[1]);
return s->cgr[1];
case 10:
DPRINTF(" cgr2 = 0x%x\n", s->cgr[2]);
return s->cgr[2];
case 18: /* LTR1 */
return 0x00004040;
case 23:
DPRINTF(" pcmr0 = 0x%x\n", s->pmcr0);
return s->pmcr0;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
return 0;
}
}
static void imx_ccm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
DPRINTF("(offset=0x%" HWADDR_PRIx ", value = 0x%x)\n",
offset, (unsigned int)value);
switch (offset >> 2) {
case 0:
s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
break;
case 1:
s->pdr0 = value & 0xff9f3fff;
break;
case 2:
s->pdr1 = value;
break;
case 4:
s->mpctl = value & 0xbfff3fff;
break;
case 6:
s->spctl = value & 0xbfff3fff;
break;
case 8:
s->cgr[0] = value;
return;
case 9:
s->cgr[1] = value;
return;
case 10:
s->cgr[2] = value;
return;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
return;
}
update_clocks(s);
}
static const struct MemoryRegionOps imx_ccm_ops = {
.read = imx_ccm_read,
.write = imx_ccm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int imx_ccm_init(SysBusDevice *dev)
{
IMXCCMState *s = IMX_CCM(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_ccm_ops, s,
TYPE_IMX_CCM, 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static int imx_ccm_post_load(void *opaque, int version_id)
{
IMXCCMState *s = (IMXCCMState *)opaque;
update_clocks(s);
return 0;
}
static void imx_ccm_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
sbc->init = imx_ccm_init;
dc->reset = imx_ccm_reset;
dc->vmsd = &vmstate_imx_ccm;
dc->desc = "i.MX Clock Control Module";
return freq;
}
static const TypeInfo imx_ccm_info = {
.name = TYPE_IMX_CCM,
.parent = TYPE_SYS_BUS_DEVICE,
.name = TYPE_IMX_CCM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXCCMState),
.class_init = imx_ccm_class_init,
.class_size = sizeof(IMXCCMClass),
.abstract = true,
};
static void imx_ccm_register_types(void)