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target/arm: Store TCR_EL* registers as uint64_t

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Change the representation of the TCR_EL* registers in the CPU state
struct from struct TCR to uint64_t.  This allows us to drop the
custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0"
checks to their more usual location in the writefn
vmsa_ttbcr_write().  We also don't need the resetfn any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-07-14 14:23:02 +01:00
parent 988cc1909f
commit cb4a0a3444
6 changed files with 27 additions and 68 deletions
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6
target/arm/internals.h
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@ -252,9 +252,9 @@ unsigned int arm_pamax(ARMCPU *cpu);
*/
static inline bool extended_addresses_enabled(CPUARMState *env)
{
TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
return arm_el_is_aa64(env, 1) ||
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
}
/* Update a QEMU watchpoint based on the information the guest has set in the
@ -790,7 +790,7 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
*/
return env->cp15.vstcr_el2;
}
return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr;
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
/**