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PPC: e500 pci host: Add support for ATMUs

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The e500 PCI controller has configurable windows that allow a guest OS
to selectively map parts of the PCI bus space to CPU address space and
to selectively map parts of the CPU address space for DMA requests into
PCI visible address ranges.

So far, we've simply assumed that this mapping is 1:1 and ignored it.

However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live
inside the first 32bits of address space. This means if we always treat
all mappings as 1:1, this map will collide with our RAM map from the CPU's
point of view.

So this patch adds proper ATMU support which allows us to keep the PCICSRBAR
below 32bits local to the PCI bus and have another, different window to PCI
BARs at the upper end of address space. We leverage this on e500plat though,
mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU.

With this patch, I can run guests with lots of RAM and not coincidently access
MSI-X mappings while I really want to access RAM.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2014-11-12 22:44:52 +01:00
parent 44045ce974
commit cb3778a045
5 changed files with 115 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/ppc/e500.c
View file

@ -288,8 +288,8 @@ static int ppce500_load_device_tree(MachineState *machine,
int len;
uint32_t pci_ranges[14] =
{
0x2000000, 0x0, 0xc0000000,
0x0, 0xc0000000,
0x2000000, 0x0, params->pci_mmio_bus_base,
params->pci_mmio_base >> 32, params->pci_mmio_base,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
@ -915,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
if (!pci_bus)
printf("couldn't create PCI controller!\n");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base);
if (pci_bus) {
/* Register network interfaces. */
for (i = 0; i < nb_nics; i++) {

2
hw/ppc/e500.h
View file

@ -19,6 +19,8 @@ typedef struct PPCE500Params {
int platform_bus_num_irqs;
hwaddr ccsrbar_base;
hwaddr pci_pio_base;
hwaddr pci_mmio_base;
hwaddr pci_mmio_bus_base;
hwaddr spin_base;
} PPCE500Params;

2
hw/ppc/e500plat.c
View file

@ -43,6 +43,8 @@ static void e500plat_init(MachineState *machine)
.platform_bus_num_irqs = 10,
.ccsrbar_base = 0xFE0000000ULL,
.pci_pio_base = 0xFE1000000ULL,
.pci_mmio_base = 0xC00000000ULL,
.pci_mmio_bus_base = 0xE0000000ULL,
.spin_base = 0xFEF000000ULL,
};

2
hw/ppc/mpc8544ds.c
View file

@ -35,6 +35,8 @@ static void mpc8544ds_init(MachineState *machine)
.fixup_devtree = mpc8544ds_fixup_devtree,
.mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
.ccsrbar_base = 0xE0000000ULL,
.pci_mmio_base = 0xC0000000ULL,
.pci_mmio_bus_base = 0xC0000000ULL,
.pci_pio_base = 0xE1000000ULL,
.spin_base = 0xEF000000ULL,
};