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aspeed queue:

Browse source 
* fix for the Aspeed I2C slave mode
 * a new I2C echo device from Klaus and its associated test in avocado.
 * initial SoC cleanups to allow the use of block devices instead of
   drives on the command line.
 * new facebook machines and eeprom fixes for the Fuji
 * readline fix
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Merge tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu into staging

aspeed queue:

* fix for the Aspeed I2C slave mode
* a new I2C echo device from Klaus and its associated test in avocado.
* initial SoC cleanups to allow the use of block devices instead of
  drives on the command line.
* new facebook machines and eeprom fixes for the Fuji
* readline fix

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# gpg: Signature made Thu 02 Mar 2023 13:03:48 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu:
  aspeed/smc: Replace SysBus IRQs with GPIO lines
  aspeed: Add a boot_rom overlap region in the SoC spi_boot container
  aspeed: Introduce a spi_boot region under the SoC
  aspeed/fuji : correct the eeprom size
  hw/at24c : modify at24c to support 1 byte address mode
  hw/arm/aspeed: Adding new machine Tiogapass in QEMU
  hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU
  tests/avocado/machine_aspeed.py: Add an I2C slave test
  hw/misc: add a toy i2c echo device
  hw/i2c: only schedule pending master when bus is idle
  readline: fix hmp completion issue

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-03-03 17:11:22 +00:00
commit cad8db9865
16 changed files with 420 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

5
include/hw/arm/aspeed_soc.h
View file

@ -58,6 +58,8 @@ struct AspeedSoCState {
MemoryRegion *dram_mr;
MemoryRegion dram_container;
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
AspeedVICState vic;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
@ -120,6 +122,7 @@ struct AspeedSoCClass {
enum {
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@ -190,6 +193,8 @@ enum {
ASPEED_DEV_JTAG1,
};
#define ASPEED_SOC_SPI_BOOT_ADDR 0x0
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);

2
include/hw/i2c/i2c.h
View file

@ -141,6 +141,8 @@ int i2c_start_send(I2CBus *bus, uint8_t address);
*/
int i2c_start_send_async(I2CBus *bus, uint8_t address);
void i2c_schedule_pending_master(I2CBus *bus);
void i2c_end_transfer(I2CBus *bus);
void i2c_nack(I2CBus *bus);
void i2c_ack(I2CBus *bus);