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target/arm: Use the constant variant of store_cpu_field() when possible

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When using a constant variable, we can replace the store_cpu_field()
call by store_cpu_field_constant() which avoid using TCG temporaries.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029231834.2476117-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-30 01:18:32 +02:00 • committed by Richard Henderson
parent daf7a1814f
commit cacb1aa486
1 changed files with 6 additions and 15 deletions
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21
target/arm/translate.c
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@ -364,8 +364,7 @@ void clear_eci_state(DisasContext *s)
* multiple insn executes. * multiple insn executes.
*/ */
if (s->eci) { if (s->eci) {
TCGv_i32 tmp = tcg_const_i32(0); store_cpu_field_constant(0, condexec_bits);
store_cpu_field(tmp, condexec_bits);
s->eci = 0; s->eci = 0;
} }
} }
@ -740,9 +739,8 @@ void gen_set_condexec(DisasContext *s)
{ {
if (s->condexec_mask) { if (s->condexec_mask) {
uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, val); store_cpu_field_constant(val, condexec_bits);
store_cpu_field(tmp, condexec_bits);
} }
} }
@ -8362,8 +8360,6 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{ {
TCGv_i32 tmp;
/* /*
* BLX <imm> would be useless on M-profile; the encoding space * BLX <imm> would be useless on M-profile; the encoding space
* is used for other insns from v8.1M onward, and UNDEFs before that. * is used for other insns from v8.1M onward, and UNDEFs before that.
@ -8377,8 +8373,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return false; return false;
} }
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
tmp = tcg_const_i32(!s->thumb); store_cpu_field_constant(!s->thumb, thumb);
store_cpu_field(tmp, thumb);
gen_jmp(s, (read_pc(s) & ~3) + a->imm); gen_jmp(s, (read_pc(s) & ~3) + a->imm);
return true; return true;
} }
@ -8677,7 +8672,6 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
* doesn't cache branch information, all we need to do is reset * doesn't cache branch information, all we need to do is reset
* FPSCR.LTPSIZE to 4. * FPSCR.LTPSIZE to 4.
*/ */
TCGv_i32 ltpsize;
if (!dc_isar_feature(aa32_lob, s) || if (!dc_isar_feature(aa32_lob, s) ||
!dc_isar_feature(aa32_mve, s)) { !dc_isar_feature(aa32_mve, s)) {
@ -8688,8 +8682,7 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
return true; return true;
} }
ltpsize = tcg_const_i32(4); store_cpu_field_constant(4, v7m.ltpsize);
store_cpu_field(ltpsize, v7m.ltpsize);
return true; return true;
} }
@ -9487,9 +9480,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
/* Reset the conditional execution bits immediately. This avoids /* Reset the conditional execution bits immediately. This avoids
complications trying to do it at the end of the block. */ complications trying to do it at the end of the block. */
if (dc->condexec_mask || dc->condexec_cond) { if (dc->condexec_mask || dc->condexec_cond) {
TCGv_i32 tmp = tcg_temp_new_i32(); store_cpu_field_constant(0, condexec_bits);
tcg_gen_movi_i32(tmp, 0);
store_cpu_field(tmp, condexec_bits);
} }
} }