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tcg: Widen gen_insn_data to uint64_t
We already pass uint64_t to restore_state_to_opc; this changes all of the other uses from insn_start through the encoding to decoding. Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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5 changed files with 45 additions and 72 deletions
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@ -723,48 +723,27 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
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#endif
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#if TARGET_INSN_START_WORDS == 1
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# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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static inline void tcg_gen_insn_start(target_ulong pc)
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{
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tcg_gen_op1(INDEX_op_insn_start, pc);
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TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
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tcg_set_insn_start_param(op, 0, pc);
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}
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# else
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static inline void tcg_gen_insn_start(target_ulong pc)
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{
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tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
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}
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# endif
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#elif TARGET_INSN_START_WORDS == 2
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# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
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{
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tcg_gen_op2(INDEX_op_insn_start, pc, a1);
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TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
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tcg_set_insn_start_param(op, 0, pc);
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tcg_set_insn_start_param(op, 1, a1);
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}
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# else
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static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
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{
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tcg_gen_op4(INDEX_op_insn_start,
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(uint32_t)pc, (uint32_t)(pc >> 32),
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(uint32_t)a1, (uint32_t)(a1 >> 32));
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}
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# endif
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#elif TARGET_INSN_START_WORDS == 3
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# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
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target_ulong a2)
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{
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tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
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TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS);
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tcg_set_insn_start_param(op, 0, pc);
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tcg_set_insn_start_param(op, 1, a1);
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tcg_set_insn_start_param(op, 2, a2);
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}
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# else
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static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
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target_ulong a2)
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{
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tcg_gen_op6(INDEX_op_insn_start,
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(uint32_t)pc, (uint32_t)(pc >> 32),
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(uint32_t)a1, (uint32_t)(a1 >> 32),
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(uint32_t)a2, (uint32_t)(a2 >> 32));
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}
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# endif
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#else
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# error "Unhandled number of operands to insn_start"
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#endif
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@ -190,7 +190,7 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
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#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
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/* QEMU specific */
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DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
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DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS,
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TCG_OPF_NOT_PRESENT)
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DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
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DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
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@ -629,7 +629,7 @@ struct TCGContext {
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TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
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uint16_t gen_insn_end_off[TCG_MAX_INSNS];
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target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
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uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
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/* Exit to translator on overflow. */
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sigjmp_buf jmp_trans;
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@ -771,24 +771,24 @@ static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
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op->args[arg] = v;
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}
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static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg)
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static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg)
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{
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#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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return tcg_get_insn_param(op, arg);
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#else
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return tcg_get_insn_param(op, arg * 2) |
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((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32);
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#endif
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if (TCG_TARGET_REG_BITS == 64) {
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return tcg_get_insn_param(op, arg);
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} else {
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return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32,
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tcg_get_insn_param(op, arg * 2 + 1));
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}
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}
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static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
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static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v)
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{
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#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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tcg_set_insn_param(op, arg, v);
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#else
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tcg_set_insn_param(op, arg * 2, v);
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tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
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#endif
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_set_insn_param(op, arg, v);
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} else {
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tcg_set_insn_param(op, arg * 2, v);
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tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
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}
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}
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/* The last op that was emitted. */
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