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hw/misc: Move NPCM7XX GCR to NPCM GCR

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A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2025-02-19 10:45:56 -08:00 • committed by Peter Maydell
parent 506af2330c
commit c99064e637
4 changed files with 59 additions and 48 deletions
Download patch file Download diff file Expand all files Collapse all files

92
hw/misc/npcm_gcr.c
View file

@ -84,10 +84,10 @@ static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
[NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4, [NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4,
}; };
static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size) static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
{ {
uint32_t reg = offset / sizeof(uint32_t); uint32_t reg = offset / sizeof(uint32_t);
NPCM7xxGCRState *s = opaque; NPCMGCRState *s = opaque;
if (reg >= NPCM7XX_GCR_NR_REGS) { if (reg >= NPCM7XX_GCR_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
@ -96,19 +96,19 @@ static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
return 0; return 0;
} }
trace_npcm7xx_gcr_read(offset, s->regs[reg]); trace_npcm_gcr_read(offset, s->regs[reg]);
return s->regs[reg]; return s->regs[reg];
} }
static void npcm7xx_gcr_write(void *opaque, hwaddr offset, static void npcm_gcr_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size) uint64_t v, unsigned size)
{ {
uint32_t reg = offset / sizeof(uint32_t); uint32_t reg = offset / sizeof(uint32_t);
NPCM7xxGCRState *s = opaque; NPCMGCRState *s = opaque;
uint32_t value = v; uint32_t value = v;
trace_npcm7xx_gcr_write(offset, value); trace_npcm_gcr_write(offset, value);
if (reg >= NPCM7XX_GCR_NR_REGS) { if (reg >= NPCM7XX_GCR_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
@ -142,9 +142,9 @@ static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
s->regs[reg] = value; s->regs[reg] = value;
} }
static const struct MemoryRegionOps npcm7xx_gcr_ops = { static const struct MemoryRegionOps npcm_gcr_ops = {
.read = npcm7xx_gcr_read, .read = npcm_gcr_read,
.write = npcm7xx_gcr_write, .write = npcm_gcr_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = { .valid = {
.min_access_size = 4, .min_access_size = 4,
@ -155,7 +155,7 @@ static const struct MemoryRegionOps npcm7xx_gcr_ops = {
static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
{ {
NPCM7xxGCRState *s = NPCM7XX_GCR(obj); NPCMGCRState *s = NPCM_GCR(obj);
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
@ -165,10 +165,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3; s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
} }
static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp) static void npcm_gcr_realize(DeviceState *dev, Error **errp)
{ {
ERRP_GUARD(); ERRP_GUARD();
NPCM7xxGCRState *s = NPCM7XX_GCR(dev); NPCMGCRState *s = NPCM_GCR(dev);
uint64_t dram_size; uint64_t dram_size;
Object *obj; Object *obj;
@ -210,55 +210,65 @@ static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8; s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
} }
static void npcm7xx_gcr_init(Object *obj) static void npcm_gcr_init(Object *obj)
{ {
NPCM7xxGCRState *s = NPCM7XX_GCR(obj); NPCMGCRState *s = NPCM_GCR(obj);
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, memory_region_init_io(&s->iomem, obj, &npcm_gcr_ops, s,
TYPE_NPCM7XX_GCR, 4 * KiB); TYPE_NPCM_GCR, 4 * KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
} }
static const VMStateDescription vmstate_npcm7xx_gcr = { static const VMStateDescription vmstate_npcm_gcr = {
.name = "npcm7xx-gcr", .name = "npcm-gcr",
.version_id = 0, .version_id = 1,
.minimum_version_id = 0, .minimum_version_id = 1,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS), VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS),
VMSTATE_END_OF_LIST(), VMSTATE_END_OF_LIST(),
}, },
}; };
static const Property npcm7xx_gcr_properties[] = { static const Property npcm_gcr_properties[] = {
DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0), DEFINE_PROP_UINT32("disabled-modules", NPCMGCRState, reset_mdlr, 0),
DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0), DEFINE_PROP_UINT32("power-on-straps", NPCMGCRState, reset_pwron, 0),
}; };
static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data) static void npcm_gcr_class_init(ObjectClass *klass, void *data)
{ {
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
dc->realize = npcm_gcr_realize;
dc->vmsd = &vmstate_npcm_gcr;
device_class_set_props(dc, npcm_gcr_properties);
}
static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END != NPCM7XX_GCR_NR_REGS);
dc->desc = "NPCM7xx System Global Control Registers"; dc->desc = "NPCM7xx System Global Control Registers";
dc->realize = npcm7xx_gcr_realize;
dc->vmsd = &vmstate_npcm7xx_gcr;
rc->phases.enter = npcm7xx_gcr_enter_reset; rc->phases.enter = npcm7xx_gcr_enter_reset;
device_class_set_props(dc, npcm7xx_gcr_properties);
} }
static const TypeInfo npcm7xx_gcr_info = { static const TypeInfo npcm_gcr_info[] = {
.name = TYPE_NPCM7XX_GCR,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxGCRState),
.instance_init = npcm7xx_gcr_init,
.class_init = npcm7xx_gcr_class_init,
};
static void npcm7xx_gcr_register_type(void)
{ {
type_register_static(&npcm7xx_gcr_info); .name = TYPE_NPCM_GCR,
} .parent = TYPE_SYS_BUS_DEVICE,
type_init(npcm7xx_gcr_register_type); .instance_size = sizeof(NPCMGCRState),
.instance_init = npcm_gcr_init,
.class_init = npcm_gcr_class_init,
.abstract = true,
},
{
.name = TYPE_NPCM7XX_GCR,
.parent = TYPE_NPCM_GCR,
.class_init = npcm7xx_gcr_class_init,
},
};
DEFINE_TYPES(npcm_gcr_info)

6
hw/misc/trace-events
View file

@ -134,9 +134,9 @@ mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%
npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm7xx_gcr.c # npcm_gcr.c
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm7xx_mft.c # npcm7xx_mft.c
npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16

2
include/hw/arm/npcm7xx.h
View file

@ -89,7 +89,7 @@ struct NPCM7xxState {
MemoryRegion ram3; MemoryRegion ram3;
MemoryRegion *dram; MemoryRegion *dram;
NPCM7xxGCRState gcr; NPCMGCRState gcr;
NPCM7xxCLKState clk; NPCM7xxCLKState clk;
NPCM7xxTimerCtrlState tim[3]; NPCM7xxTimerCtrlState tim[3];
NPCM7xxADCState adc; NPCM7xxADCState adc;

7
include/hw/misc/npcm_gcr.h
View file

@ -55,7 +55,7 @@
*/ */
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
struct NPCM7xxGCRState { typedef struct NPCMGCRState {
SysBusDevice parent; SysBusDevice parent;
MemoryRegion iomem; MemoryRegion iomem;
@ -65,9 +65,10 @@ struct NPCM7xxGCRState {
uint32_t reset_pwron; uint32_t reset_pwron;
uint32_t reset_mdlr; uint32_t reset_mdlr;
uint32_t reset_intcr3; uint32_t reset_intcr3;
}; } NPCMGCRState;
#define TYPE_NPCM_GCR "npcm-gcr"
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr" #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR)
#endif /* NPCM_GCR_H */ #endif /* NPCM_GCR_H */