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hw/misc: Move NPCM7XX GCR to NPCM GCR
A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-6-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu
Peter Maydell
parent
506af2330c
commit
c99064e637
4 changed files with 59 additions and 48 deletions
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@ -84,10 +84,10 @@ static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
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[NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4,
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};
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static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
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static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxGCRState *s = opaque;
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NPCMGCRState *s = opaque;
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if (reg >= NPCM7XX_GCR_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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@ -96,19 +96,19 @@ static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
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return 0;
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}
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trace_npcm7xx_gcr_read(offset, s->regs[reg]);
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trace_npcm_gcr_read(offset, s->regs[reg]);
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return s->regs[reg];
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}
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static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
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static void npcm_gcr_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxGCRState *s = opaque;
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NPCMGCRState *s = opaque;
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uint32_t value = v;
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trace_npcm7xx_gcr_write(offset, value);
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trace_npcm_gcr_write(offset, value);
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if (reg >= NPCM7XX_GCR_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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@ -142,9 +142,9 @@ static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
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s->regs[reg] = value;
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}
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static const struct MemoryRegionOps npcm7xx_gcr_ops = {
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.read = npcm7xx_gcr_read,
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.write = npcm7xx_gcr_write,
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static const struct MemoryRegionOps npcm_gcr_ops = {
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.read = npcm_gcr_read,
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.write = npcm_gcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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@ -155,7 +155,7 @@ static const struct MemoryRegionOps npcm7xx_gcr_ops = {
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static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
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NPCMGCRState *s = NPCM_GCR(obj);
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QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
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@ -165,10 +165,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
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s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
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}
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static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
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static void npcm_gcr_realize(DeviceState *dev, Error **errp)
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{
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ERRP_GUARD();
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NPCM7xxGCRState *s = NPCM7XX_GCR(dev);
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NPCMGCRState *s = NPCM_GCR(dev);
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uint64_t dram_size;
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Object *obj;
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@ -210,55 +210,65 @@ static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
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s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
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}
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static void npcm7xx_gcr_init(Object *obj)
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static void npcm_gcr_init(Object *obj)
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{
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NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
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NPCMGCRState *s = NPCM_GCR(obj);
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memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
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TYPE_NPCM7XX_GCR, 4 * KiB);
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memory_region_init_io(&s->iomem, obj, &npcm_gcr_ops, s,
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TYPE_NPCM_GCR, 4 * KiB);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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}
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static const VMStateDescription vmstate_npcm7xx_gcr = {
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.name = "npcm7xx-gcr",
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.version_id = 0,
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.minimum_version_id = 0,
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static const VMStateDescription vmstate_npcm_gcr = {
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.name = "npcm-gcr",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS),
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VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static const Property npcm7xx_gcr_properties[] = {
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DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0),
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DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0),
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static const Property npcm_gcr_properties[] = {
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DEFINE_PROP_UINT32("disabled-modules", NPCMGCRState, reset_mdlr, 0),
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DEFINE_PROP_UINT32("power-on-straps", NPCMGCRState, reset_pwron, 0),
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};
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static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
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static void npcm_gcr_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
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dc->realize = npcm_gcr_realize;
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dc->vmsd = &vmstate_npcm_gcr;
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device_class_set_props(dc, npcm_gcr_properties);
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}
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static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END != NPCM7XX_GCR_NR_REGS);
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dc->desc = "NPCM7xx System Global Control Registers";
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dc->realize = npcm7xx_gcr_realize;
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dc->vmsd = &vmstate_npcm7xx_gcr;
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rc->phases.enter = npcm7xx_gcr_enter_reset;
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device_class_set_props(dc, npcm7xx_gcr_properties);
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}
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static const TypeInfo npcm7xx_gcr_info = {
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.name = TYPE_NPCM7XX_GCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxGCRState),
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.instance_init = npcm7xx_gcr_init,
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.class_init = npcm7xx_gcr_class_init,
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static const TypeInfo npcm_gcr_info[] = {
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{
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.name = TYPE_NPCM_GCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCMGCRState),
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.instance_init = npcm_gcr_init,
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.class_init = npcm_gcr_class_init,
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.abstract = true,
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},
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{
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.name = TYPE_NPCM7XX_GCR,
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.parent = TYPE_NPCM_GCR,
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.class_init = npcm7xx_gcr_class_init,
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},
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};
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static void npcm7xx_gcr_register_type(void)
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{
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type_register_static(&npcm7xx_gcr_info);
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}
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type_init(npcm7xx_gcr_register_type);
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DEFINE_TYPES(npcm_gcr_info)
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@ -134,9 +134,9 @@ mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%
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npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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# npcm7xx_gcr.c
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npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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# npcm_gcr.c
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npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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# npcm7xx_mft.c
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npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
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@ -89,7 +89,7 @@ struct NPCM7xxState {
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MemoryRegion ram3;
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MemoryRegion *dram;
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NPCM7xxGCRState gcr;
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NPCMGCRState gcr;
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NPCM7xxCLKState clk;
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NPCM7xxTimerCtrlState tim[3];
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NPCM7xxADCState adc;
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@ -55,7 +55,7 @@
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*/
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#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
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struct NPCM7xxGCRState {
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typedef struct NPCMGCRState {
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SysBusDevice parent;
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MemoryRegion iomem;
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@ -65,9 +65,10 @@ struct NPCM7xxGCRState {
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uint32_t reset_pwron;
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uint32_t reset_mdlr;
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uint32_t reset_intcr3;
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};
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} NPCMGCRState;
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#define TYPE_NPCM_GCR "npcm-gcr"
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#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
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OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR)
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#endif /* NPCM_GCR_H */
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