motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Merge INDEX_op_ctz_{i32,i64}

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-08 17:07:01 -08:00
parent e3fcde59c9
commit c96447d838
7 changed files with 20 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

2
docs/devel/tcg-ops.rst
View file

@ -362,7 +362,7 @@ Logical
- | *t0* = *t1* ? clz(*t1*) : *t2* - | *t0* = *t1* ? clz(*t1*) : *t2*
* - ctz_i32/i64 *t0*, *t1*, *t2* * - ctz *t0*, *t1*, *t2*
- | *t0* = *t1* ? ctz(*t1*) : *t2* - | *t0* = *t1* ? ctz(*t1*) : *t2*

3
include/tcg/tcg-opc.h
View file

@ -43,6 +43,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT)
DEF(and, 1, 2, 0, TCG_OPF_INT) DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT) DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(clz, 1, 2, 0, TCG_OPF_INT) DEF(clz, 1, 2, 0, TCG_OPF_INT)
DEF(ctz, 1, 2, 0, TCG_OPF_INT)
DEF(divs, 1, 2, 0, TCG_OPF_INT) DEF(divs, 1, 2, 0, TCG_OPF_INT)
DEF(divs2, 2, 3, 0, TCG_OPF_INT) DEF(divs2, 2, 3, 0, TCG_OPF_INT)
DEF(divu, 1, 2, 0, TCG_OPF_INT) DEF(divu, 1, 2, 0, TCG_OPF_INT)
@ -96,7 +97,6 @@ DEF(setcond2_i32, 1, 4, 1, 0)
DEF(bswap16_i32, 1, 1, 1, 0) DEF(bswap16_i32, 1, 1, 1, 0)
DEF(bswap32_i32, 1, 1, 1, 0) DEF(bswap32_i32, 1, 1, 1, 0)
DEF(ctz_i32, 1, 2, 0, 0)
DEF(ctpop_i32, 1, 1, 0, 0) DEF(ctpop_i32, 1, 1, 0, 0)
DEF(setcond_i64, 1, 2, 1, 0) DEF(setcond_i64, 1, 2, 1, 0)
@ -130,7 +130,6 @@ DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(bswap16_i64, 1, 1, 1, 0) DEF(bswap16_i64, 1, 1, 1, 0)
DEF(bswap32_i64, 1, 1, 1, 0) DEF(bswap32_i64, 1, 1, 1, 0)
DEF(bswap64_i64, 1, 1, 1, 0) DEF(bswap64_i64, 1, 1, 1, 0)
DEF(ctz_i64, 1, 2, 0, 0)
DEF(ctpop_i64, 1, 1, 0, 0) DEF(ctpop_i64, 1, 1, 0, 0)
DEF(add2_i64, 2, 4, 0, 0) DEF(add2_i64, 2, 4, 0, 0)

10
tcg/optimize.c
View file

@ -509,10 +509,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
} }
return x ? clz64(x) : y; return x ? clz64(x) : y;
case INDEX_op_ctz_i32: case INDEX_op_ctz:
return (uint32_t)x ? ctz32(x) : y; if (type == TCG_TYPE_I32) {
return (uint32_t)x ? ctz32(x) : y;
case INDEX_op_ctz_i64: }
return x ? ctz64(x) : y; return x ? ctz64(x) : y;
case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i32:
@ -2899,7 +2899,7 @@ void tcg_optimize(TCGContext *s)
done = fold_bswap(&ctx, op); done = fold_bswap(&ctx, op);
break; break;
case INDEX_op_clz: case INDEX_op_clz:
CASE_OP_32_64(ctz): case INDEX_op_ctz:
done = fold_count_zeros(&ctx, op); done = fold_count_zeros(&ctx, op);
break; break;
CASE_OP_32_64(ctpop): CASE_OP_32_64(ctpop):

16
tcg/tcg-op.c
View file

@ -750,11 +750,11 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
TCGv_i32 z, t; TCGv_i32 z, t;
if (tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0)) { if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_ctz_i32, ret, arg1, arg2); tcg_gen_op3_i32(INDEX_op_ctz, ret, arg1, arg2);
return; return;
} }
if (tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0)) { if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) {
TCGv_i64 t1 = tcg_temp_ebb_new_i64(); TCGv_i64 t1 = tcg_temp_ebb_new_i64();
TCGv_i64 t2 = tcg_temp_ebb_new_i64(); TCGv_i64 t2 = tcg_temp_ebb_new_i64();
tcg_gen_extu_i32_i64(t1, arg1); tcg_gen_extu_i32_i64(t1, arg1);
@ -788,7 +788,7 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
{ {
if (!tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0) if (!tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)
&& TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) { && TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) {
/* This equivalence has the advantage of not requiring a fixup. */ /* This equivalence has the advantage of not requiring a fixup. */
TCGv_i32 t = tcg_temp_ebb_new_i32(); TCGv_i32 t = tcg_temp_ebb_new_i32();
@ -2366,8 +2366,8 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{ {
TCGv_i64 z, t; TCGv_i64 z, t;
if (tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0)) { if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_ctz_i64, ret, arg1, arg2); tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2);
return; return;
} }
if (TCG_TARGET_HAS_ctpop_i64) { if (TCG_TARGET_HAS_ctpop_i64) {
@ -2395,7 +2395,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
{ {
if (TCG_TARGET_REG_BITS == 32 if (TCG_TARGET_REG_BITS == 32
&& arg2 <= 0xffffffffu && arg2 <= 0xffffffffu
&& tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0)) { && tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) {
TCGv_i32 t32 = tcg_temp_ebb_new_i32(); TCGv_i32 t32 = tcg_temp_ebb_new_i32();
tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32);
tcg_gen_addi_i32(t32, t32, 32); tcg_gen_addi_i32(t32, t32, 32);
@ -2403,7 +2403,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_movi_i32(TCGV_HIGH(ret), 0); tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
tcg_temp_free_i32(t32); tcg_temp_free_i32(t32);
} else if (arg2 == 64 } else if (arg2 == 64
&& !tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0) && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)
&& TCG_TARGET_HAS_ctpop_i64) { && TCG_TARGET_HAS_ctpop_i64) {
/* This equivalence has the advantage of not requiring a fixup. */ /* This equivalence has the advantage of not requiring a fixup. */
TCGv_i64 t = tcg_temp_ebb_new_i64(); TCGv_i64 t = tcg_temp_ebb_new_i64();

6
tcg/tcg.c
View file

@ -1027,8 +1027,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
OUTOP(INDEX_op_ctz_i32, TCGOutOpBinary, outop_ctz), OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
OUTOP(INDEX_op_ctz_i64, TCGOutOpBinary, outop_ctz),
OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu),
OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2),
@ -5400,8 +5399,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_and: case INDEX_op_and:
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_clz: case INDEX_op_clz:
case INDEX_op_ctz_i32: case INDEX_op_ctz:
case INDEX_op_ctz_i64:
case INDEX_op_divs: case INDEX_op_divs:
case INDEX_op_divu: case INDEX_op_divu:
case INDEX_op_eqv: case INDEX_op_eqv:

4
tcg/tci.c
View file

@ -735,7 +735,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
break; break;
case INDEX_op_ctz_i64: case INDEX_op_ctz:
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
break; break;
@ -1049,6 +1049,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_and: case INDEX_op_and:
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_clz: case INDEX_op_clz:
case INDEX_op_ctz:
case INDEX_op_divs: case INDEX_op_divs:
case INDEX_op_divu: case INDEX_op_divu:
case INDEX_op_eqv: case INDEX_op_eqv:
@ -1066,7 +1067,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_shr: case INDEX_op_shr:
case INDEX_op_sub: case INDEX_op_sub:
case INDEX_op_xor: case INDEX_op_xor:
case INDEX_op_ctz_i64:
case INDEX_op_tci_ctz32: case INDEX_op_tci_ctz32:
case INDEX_op_tci_clz32: case INDEX_op_tci_clz32:
case INDEX_op_tci_divs32: case INDEX_op_tci_divs32:

2
tcg/tci/tcg-target.c.inc
View file

@ -645,7 +645,7 @@ static void tgen_ctz(TCGContext *s, TCGType type,
{ {
TCGOpcode opc = (type == TCG_TYPE_I32 TCGOpcode opc = (type == TCG_TYPE_I32
? INDEX_op_tci_ctz32 ? INDEX_op_tci_ctz32
: INDEX_op_ctz_i64); : INDEX_op_ctz);
tcg_out_op_rrr(s, opc, a0, a1, a2); tcg_out_op_rrr(s, opc, a0, a1, a2);
} }