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RISC-V: Adding XTheadBa ISA extension

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This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:02 +01:00 • committed by Alistair Francis
parent 134c3ffa34
commit c9410a689f
5 changed files with 66 additions and 1 deletions
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39
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -16,6 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_XTHEADBA(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadba) { \
return false; \
} \
} while (0)
#define REQUIRE_XTHEADCMO(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadcmo) { \
return false; \
@ -28,6 +34,39 @@
} \
} while (0)
/* XTheadBa */
/*
* th.addsl is similar to sh[123]add (from Zba), but not an
* alternative encoding: while sh[123] applies the shift to rs1,
* th.addsl shifts rs2.
*/
#define GEN_TH_ADDSL(SHAMT) \
static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
TCGv t = tcg_temp_new(); \
tcg_gen_shli_tl(t, arg2, SHAMT); \
tcg_gen_add_tl(ret, t, arg1); \
tcg_temp_free(t); \
}
GEN_TH_ADDSL(1)
GEN_TH_ADDSL(2)
GEN_TH_ADDSL(3)
#define GEN_TRANS_TH_ADDSL(SHAMT) \
static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
arg_th_addsl##SHAMT * a) \
{ \
REQUIRE_XTHEADBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
}
GEN_TRANS_TH_ADDSL(1)
GEN_TRANS_TH_ADDSL(2)
GEN_TRANS_TH_ADDSL(3)
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)