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target/arm: Use the max page size in a 2-stage ptw

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We had only been reporting the stage2 page size.  This causes
problems if stage1 is using a larger page size (16k, 2M, etc),
but stage2 is using a smaller page size, because cputlb does
not set large_page_{addr,mask} properly.

Fix by using the max of the two page sizes.

Reported-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-24 15:18:51 +10:00 • committed by Peter Maydell
parent 65c123fdf5
commit c8d6c286ab
1 changed files with 10 additions and 1 deletions
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11
target/arm/ptw.c
View file

@ -2571,7 +2571,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
ARMMMUFaultInfo *fi) ARMMMUFaultInfo *fi)
{ {
hwaddr ipa; hwaddr ipa;
int s1_prot; int s1_prot, s1_lgpgsz;
bool is_secure = ptw->in_secure; bool is_secure = ptw->in_secure;
bool ret, ipa_secure, s2walk_secure; bool ret, ipa_secure, s2walk_secure;
ARMCacheAttrs cacheattrs1; ARMCacheAttrs cacheattrs1;
@ -2607,6 +2607,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
* Save the stage1 results so that we may merge prot and cacheattrs later. * Save the stage1 results so that we may merge prot and cacheattrs later.
*/ */
s1_prot = result->f.prot; s1_prot = result->f.prot;
s1_lgpgsz = result->f.lg_page_size;
cacheattrs1 = result->cacheattrs; cacheattrs1 = result->cacheattrs;
memset(result, 0, sizeof(*result)); memset(result, 0, sizeof(*result));
@ -2621,6 +2622,14 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
return ret; return ret;
} }
/*
* Use the maximum of the S1 & S2 page size, so that invalidation
* of pages > TARGET_PAGE_SIZE works correctly.
*/
if (result->f.lg_page_size < s1_lgpgsz) {
result->f.lg_page_size = s1_lgpgsz;
}
/* Combine the S1 and S2 cache attributes. */ /* Combine the S1 and S2 cache attributes. */
hcr = arm_hcr_el2_eff_secstate(env, is_secure); hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if (hcr & HCR_DC) { if (hcr & HCR_DC) {