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target-ppc: Add XML files for PowerPC registers

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These files are nearly identical to the XML files provided with GDB.
The only difference is that power-{fpu,spe}.xml do not assign register
numbers; the internal QEMU machinery takes care of that.

Define gdb_xml_files for ppc targets in configure as well.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6420 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-01-24 15:07:34 +00:00
parent 0ccff151b4
commit c8b3532d8a
6 changed files with 248 additions and 0 deletions
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57
gdb-xml/power-altivec.xml Normal file
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<?xml version="1.0"?>
<!-- Copyright (C) 2007, 2008 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.power.altivec">
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v16i8" type="int8" count="16"/>
<union id="vec128">
<field name="uint128" type="uint128"/>
<field name="v4_float" type="v4f"/>
<field name="v4_int32" type="v4i32"/>
<field name="v8_int16" type="v8i16"/>
<field name="v16_int8" type="v16i8"/>
</union>
<reg name="vr0" bitsize="128" type="vec128"/>
<reg name="vr1" bitsize="128" type="vec128"/>
<reg name="vr2" bitsize="128" type="vec128"/>
<reg name="vr3" bitsize="128" type="vec128"/>
<reg name="vr4" bitsize="128" type="vec128"/>
<reg name="vr5" bitsize="128" type="vec128"/>
<reg name="vr6" bitsize="128" type="vec128"/>
<reg name="vr7" bitsize="128" type="vec128"/>
<reg name="vr8" bitsize="128" type="vec128"/>
<reg name="vr9" bitsize="128" type="vec128"/>
<reg name="vr10" bitsize="128" type="vec128"/>
<reg name="vr11" bitsize="128" type="vec128"/>
<reg name="vr12" bitsize="128" type="vec128"/>
<reg name="vr13" bitsize="128" type="vec128"/>
<reg name="vr14" bitsize="128" type="vec128"/>
<reg name="vr15" bitsize="128" type="vec128"/>
<reg name="vr16" bitsize="128" type="vec128"/>
<reg name="vr17" bitsize="128" type="vec128"/>
<reg name="vr18" bitsize="128" type="vec128"/>
<reg name="vr19" bitsize="128" type="vec128"/>
<reg name="vr20" bitsize="128" type="vec128"/>
<reg name="vr21" bitsize="128" type="vec128"/>
<reg name="vr22" bitsize="128" type="vec128"/>
<reg name="vr23" bitsize="128" type="vec128"/>
<reg name="vr24" bitsize="128" type="vec128"/>
<reg name="vr25" bitsize="128" type="vec128"/>
<reg name="vr26" bitsize="128" type="vec128"/>
<reg name="vr27" bitsize="128" type="vec128"/>
<reg name="vr28" bitsize="128" type="vec128"/>
<reg name="vr29" bitsize="128" type="vec128"/>
<reg name="vr30" bitsize="128" type="vec128"/>
<reg name="vr31" bitsize="128" type="vec128"/>
<reg name="vscr" bitsize="32" group="vector"/>
<reg name="vrsave" bitsize="32" group="vector"/>
</feature>