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target/loongarch: Separate the hardware flags into MMU index and PLV

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Regarding the patchset v3 has been merged into main line, and not
approved, this patch updates to patchset v4.

Fixes: b4bda200 ("target/loongarch: Adjust the layout of hardware flags bit fields")
Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221107024526.702297-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Rui Wang 2022-11-07 10:45:25 +08:00 • committed by Song Gao
parent 466e81ff12
commit c8885b8839
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GPG key ID: 40A2FFF239263EDF
5 changed files with 18 additions and 16 deletions
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4
target/loongarch/tlb_helper.c
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@ -170,8 +170,8 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
int user_mode = mmu_idx == MMU_USER_IDX;
int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
int user_mode = mmu_idx == MMU_IDX_USER;
int kernel_mode = mmu_idx == MMU_IDX_KERNEL;
uint32_t plv, base_c, base_v;
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);