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target/loongarch: Separate the hardware flags into MMU index and PLV

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Regarding the patchset v3 has been merged into main line, and not
approved, this patch updates to patchset v4.

Fixes: b4bda200 ("target/loongarch: Adjust the layout of hardware flags bit fields")
Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221107024526.702297-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Rui Wang 2022-11-07 10:45:25 +08:00 • committed by Song Gao
parent 466e81ff12
commit c8885b8839
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GPG key ID: 40A2FFF239263EDF
5 changed files with 18 additions and 16 deletions
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18
target/loongarch/cpu.h
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@ -374,21 +374,21 @@ struct LoongArchCPUClass {
* 0 for kernel mode, 3 for user mode.
* Define an extra index for DA(direct addressing) mode.
*/
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_DA_IDX 4
#define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3
#define MMU_IDX_KERNEL MMU_PLV_KERNEL
#define MMU_IDX_USER MMU_PLV_USER
#define MMU_IDX_DA 4
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
return MMU_IDX_USER;
#else
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
if (!pg) {
return MMU_DA_IDX;
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
}
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
return MMU_IDX_DA;
#endif
}