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target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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3 changed files with 22 additions and 13 deletions
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@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState {
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target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
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target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
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uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
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uint32_t vr; /* Version register */
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uint32_t upr; /* Unit presence register */
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uint32_t dmmucfgr; /* DMMU configure register */
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uint32_t immucfgr; /* IMMU configure register */
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uint32_t esr; /* Exception supervisor register */
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uint32_t evbar; /* Exception vector base address register */
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uint32_t pmr; /* Power Management Register */
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@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState {
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struct {} end_reset_fields;
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/* Fields from here on are preserved across CPU reset. */
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uint32_t vr; /* Version register */
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uint32_t upr; /* Unit presence register */
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uint32_t cpucfgr; /* CPU configure register */
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uint32_t dmmucfgr; /* DMMU configure register */
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uint32_t immucfgr; /* IMMU configure register */
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#ifndef CONFIG_USER_ONLY
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QEMUTimer *timer;
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