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target/riscv: Add the force HS exception mode

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Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit
specifies if an exeption should be taken to HS mode no matter the
current delegation status. This is used when an exeption must be taken
to HS mode, such as when handling interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:01:54 -08:00 • committed by Palmer Dabbelt
parent ef6bb7b626
commit c7b1bbc80f
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3 changed files with 26 additions and 0 deletions
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18
target/riscv/cpu_helper.c
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@ -100,6 +100,24 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
}
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, FORCE_HS_EXCEP);
}
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;