motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 08:43:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)

Browse source 
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 14:22:32 +02:00
parent f18708a53a
commit c79db8c239
2 changed files with 9 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

3
target/mips/tcg/msa.decode
View file

@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
BINSL 011110 110.. ..... ..... ..... 001101 @3r
BINSR 011110 111.. ..... ..... ..... 001101 @3r
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r