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target/arm: Remove fp_status_f16_a64

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Replace with fp_status[FPST_A64_F16].

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250129013857.135256-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-01 16:40:05 +00:00 • committed by Peter Maydell
parent ee4316f65b
commit c71296565c
5 changed files with 14 additions and 16 deletions
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2
target/arm/cpu.c
View file

@ -554,7 +554,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]);
arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]);
set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]);

1
target/arm/cpu.h
View file

@ -693,7 +693,6 @@ typedef struct CPUArchState {
float_status fp_status_a32;
float_status fp_status_a64;
float_status fp_status_f16_a32;
float_status fp_status_f16_a64;
};
};

2
target/arm/tcg/sme_helper.c
View file

@ -1043,7 +1043,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
* produces default NaNs. We also need a second copy of fp_status with
* round-to-odd -- see above.
*/
fpst_f16 = env->vfp.fp_status_f16_a64;
fpst_f16 = env->vfp.fp_status[FPST_A64_F16];
fpst_std = env->vfp.fp_status_a64;
set_default_nan_mode(true, &fpst_std);
set_default_nan_mode(true, &fpst_f16);

9
target/arm/tcg/vec_helper.c
View file

@ -2173,7 +2173,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
}
}
do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, negx, negf, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64));
get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
}
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
@ -2183,7 +2183,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
bool is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
float_status *status = &env->vfp.fp_status_a64;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
int negx = 0, negf = 0;
if (is_s) {
@ -2254,7 +2254,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
}
}
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, negx, negf, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64));
get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
}
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
@ -2265,7 +2265,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
float_status *status = &env->vfp.fp_status_a64;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
int negx = 0, negf = 0;
if (is_s) {
@ -2275,7 +2275,6 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
negx = 0x8000;
}
}
for (i = 0; i < oprsz; i += 16) {
float16 mm_16 = *(float16 *)(vm + i + idx);
float32 mm = float16_to_float32_by_bits(mm_16, fz16);

16
target/arm/vfp_helper.c
View file

@ -126,7 +126,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
& ~float_flag_input_denormal_flushed);
a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64);
a64_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16])
& ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used));
/*
* We do not merge in flags from FPST_AH or FPST_AH_F16, because
@ -158,7 +158,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16_a32);
set_float_exception_flags(0, &env->vfp.fp_status_f16_a64);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]);
@ -201,16 +201,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]);
}
if (changed & FPCR_FZ16) {
bool ftz_enabled = val & FPCR_FZ16;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]);
}
@ -235,7 +235,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]);
}
@ -245,10 +245,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
if (ah_enabled) {
/* Change behaviours for A64 FP operations */
arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_ah_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
} else {
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
}
}
/*