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target/arm: use FIELD macro for CNTHCTL bit definitions
We prefer the FIELD macro over ad-hoc #defines for register bits; switch CNTHCTL to that style before we add any more bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
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2 changed files with 29 additions and 7 deletions
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@ -2652,8 +2652,8 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
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* It is RES0 in Secure and NonSecure state.
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*/
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if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
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((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
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(timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
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((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
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(timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
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irqstate = 0;
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}
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@ -2968,12 +2968,11 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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ARMCPU *cpu = env_archcpu(env);
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uint32_t oldval = env->cp15.cnthctl_el2;
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raw_write(env, ri, value);
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if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
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if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
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gt_update_irq(cpu, GTIMER_VIRT);
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} else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
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} else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
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gt_update_irq(cpu, GTIMER_PHYS);
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}
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}
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