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https://github.com/Motorhead1991/qemu.git
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LoongArch updates:
Store value in SET_FPU_* macros. Fix unused variable Werrors in acpi-build.c Update xml to match upstream gdb. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmLtdTodHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/u3Qf/XON//wiT054wyL3a wCZ7c4A96zA0Zu+S1FSo4CZ81wCUpAF5b76fhIU5GrLuWrs/UzOcn+akS8LNLLcM nQHqbYNQbkTGOj6DwlZfts8Ul/Ki/Yimjh0gBLFGepzYrsahJ4dCVwQR/KZNkMKf xwBn3+yq96DzEmIqjqEQtlet3Wmsow/zDU+RuHbtdrFiSx6MwhLo/e+dHVEEPkEL EBmFNETcmAzIg+oFfifkP1ZHgL/Nt2yjElwFZM2pKLMgANVpHOpCTap03KAO/xTt LzX5nmJ+4MYPyoEchRaNuq5sB5GqicDGuwGPdhu6qOV589duZ64M4dfm9ErTKEFA eE27rA== =fcsy -----END PGP SIGNATURE----- Merge tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu into staging LoongArch updates: Store value in SET_FPU_* macros. Fix unused variable Werrors in acpi-build.c Update xml to match upstream gdb. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmLtdTodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/u3Qf/XON//wiT054wyL3a # wCZ7c4A96zA0Zu+S1FSo4CZ81wCUpAF5b76fhIU5GrLuWrs/UzOcn+akS8LNLLcM # nQHqbYNQbkTGOj6DwlZfts8Ul/Ki/Yimjh0gBLFGepzYrsahJ4dCVwQR/KZNkMKf # xwBn3+yq96DzEmIqjqEQtlet3Wmsow/zDU+RuHbtdrFiSx6MwhLo/e+dHVEEPkEL # EBmFNETcmAzIg+oFfifkP1ZHgL/Nt2yjElwFZM2pKLMgANVpHOpCTap03KAO/xTt # LzX5nmJ+4MYPyoEchRaNuq5sB5GqicDGuwGPdhu6qOV589duZ64M4dfm9ErTKEFA # eE27rA== # =fcsy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 05 Aug 2022 12:53:30 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu: target/loongarch: Update gdb_set_fpu() and gdb_get_fpu() target/loongarch: Update loongarch-fpu.xml target/loongarch: update loongarch-base64.xml target/loongarch: add gdb_arch_name() target/loongarch: Fix GDB get the wrong pc hw/loongarch: remove acpi-build.c unused variable 'aml_len' target/loongarch: Fix macros SET_FPU_* in cpu.h Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
c669f22f1a
10 changed files with 119 additions and 110 deletions
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@ -661,6 +661,11 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
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};
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#endif
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static gchar *loongarch_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("loongarch64");
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}
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static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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{
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LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
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@ -683,9 +688,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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cc->gdb_read_register = loongarch_cpu_gdb_read_register;
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cc->gdb_write_register = loongarch_cpu_gdb_write_register;
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cc->disas_set_info = loongarch_cpu_disas_set_info;
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cc->gdb_num_core_regs = 34;
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "loongarch-base64.xml";
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cc->gdb_stop_before_watchpoint = true;
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cc->gdb_arch_name = loongarch_gdb_arch_name;
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#ifdef CONFIG_TCG
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cc->tcg_ops = &loongarch_tcg_ops;
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@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
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FIELD(FCSR0, CAUSE, 24, 5)
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#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
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#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V)
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#define SET_FP_CAUSE(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
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} while (0)
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#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
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#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
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#define SET_FP_ENABLES(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
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} while (0)
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#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
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#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V)
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#define SET_FP_FLAGS(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
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} while (0)
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#define UPDATE_FP_FLAGS(REG, V) \
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do { \
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(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
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@ -11,6 +11,24 @@
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#include "internals.h"
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#include "exec/gdbstub.h"
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uint64_t read_fcc(CPULoongArchState *env)
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{
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uint64_t ret = 0;
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for (int i = 0; i < 8; ++i) {
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ret |= (uint64_t)env->cf[i] << (i * 8);
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}
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return ret;
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}
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void write_fcc(CPULoongArchState *env, uint64_t val)
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{
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for (int i = 0; i < 8; ++i) {
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env->cf[i] = (val >> (i * 8)) & 1;
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}
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}
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int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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@ -19,8 +37,11 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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if (0 <= n && n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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/* orig_a0 */
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return gdb_get_regl(mem_buf, 0);
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} else if (n == 33) {
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return gdb_get_regl(mem_buf, env->pc);
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} else if (n == 34) {
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return gdb_get_regl(mem_buf, env->CSR_BADV);
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}
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return 0;
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@ -36,7 +57,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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if (0 <= n && n < 32) {
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env->gpr[n] = tmp;
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length = sizeof(target_ulong);
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} else if (n == 32) {
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} else if (n == 33) {
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env->pc = tmp;
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length = sizeof(target_ulong);
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}
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@ -48,9 +69,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
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{
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if (0 <= n && n < 32) {
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return gdb_get_reg64(mem_buf, env->fpr[n]);
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} else if (32 <= n && n < 40) {
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return gdb_get_reg8(mem_buf, env->cf[n - 32]);
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} else if (n == 40) {
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} else if (n == 32) {
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uint64_t val = read_fcc(env);
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return gdb_get_reg64(mem_buf, val);
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} else if (n == 33) {
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return gdb_get_reg32(mem_buf, env->fcsr0);
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}
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return 0;
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@ -64,10 +86,11 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
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if (0 <= n && n < 32) {
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env->fpr[n] = ldq_p(mem_buf);
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length = 8;
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} else if (32 <= n && n < 40) {
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env->cf[n - 32] = ldub_p(mem_buf);
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length = 1;
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} else if (n == 40) {
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} else if (n == 32) {
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uint64_t val = ldq_p(mem_buf);
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write_fcc(env, val);
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length = 8;
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} else if (n == 33) {
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env->fcsr0 = ldl_p(mem_buf);
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length = 4;
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}
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@ -77,5 +100,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
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void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
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41, "loongarch-fpu64.xml", 0);
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41, "loongarch-fpu.xml", 0);
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}
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@ -51,6 +51,9 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif /* !CONFIG_USER_ONLY */
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uint64_t read_fcc(CPULoongArchState *env);
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void write_fcc(CPULoongArchState *env, uint64_t val);
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int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
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int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
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void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
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