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target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions

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Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alexey Baturo 2021-10-25 20:36:07 +03:00 • committed by Alistair Francis
parent bd5594ca28
commit c655df7fe0
5 changed files with 17 additions and 0 deletions
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2
target/riscv/insn_trans/trans_rvi.c.inc
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@ -144,6 +144,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest);
@ -185,6 +186,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;