hw/intc/aspeed: Support setting different memory size

According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.

Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:10 +08:00 committed by Cédric Le Goater
parent 8dd163f915
commit c5728c3488
2 changed files with 11 additions and 1 deletions

View file

@ -302,10 +302,16 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i; int i;
memory_region_init(&s->iomem_container, OBJECT(s),
TYPE_ASPEED_INTC ".container", aic->mem_size);
sysbus_init_mmio(sbd, &s->iomem_container);
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2); TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
sysbus_init_mmio(sbd, &s->iomem); memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
for (i = 0; i < aic->num_ints; i++) { for (i = 0; i < aic->num_ints; i++) {
@ -344,6 +350,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC Controller"; dc->desc = "ASPEED 2700 INTC Controller";
aic->num_lines = 32; aic->num_lines = 32;
aic->num_ints = 9; aic->num_ints = 9;
aic->mem_size = 0x4000;
} }
static const TypeInfo aspeed_2700_intc_info = { static const TypeInfo aspeed_2700_intc_info = {

View file

@ -25,6 +25,8 @@ struct AspeedINTCState {
/*< public >*/ /*< public >*/
MemoryRegion iomem; MemoryRegion iomem;
MemoryRegion iomem_container;
uint32_t regs[ASPEED_INTC_NR_REGS]; uint32_t regs[ASPEED_INTC_NR_REGS];
OrIRQState orgates[ASPEED_INTC_NR_INTS]; OrIRQState orgates[ASPEED_INTC_NR_INTS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS];
@ -39,6 +41,7 @@ struct AspeedINTCClass {
uint32_t num_lines; uint32_t num_lines;
uint32_t num_ints; uint32_t num_ints;
uint64_t mem_size;
}; };
#endif /* ASPEED_INTC_H */ #endif /* ASPEED_INTC_H */