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hw/intc/aspeed: Support setting different memory size
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB (0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400) of register space. Introduced a new class attribute "mem_size" to set different memory sizes for the INTC models in AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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2 changed files with 11 additions and 1 deletions
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@ -302,10 +302,16 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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int i;
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int i;
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memory_region_init(&s->iomem_container, OBJECT(s),
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TYPE_ASPEED_INTC ".container", aic->mem_size);
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sysbus_init_mmio(sbd, &s->iomem_container);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
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TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
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TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
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sysbus_init_mmio(sbd, &s->iomem);
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memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
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qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
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qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
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for (i = 0; i < aic->num_ints; i++) {
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for (i = 0; i < aic->num_ints; i++) {
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@ -344,6 +350,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
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dc->desc = "ASPEED 2700 INTC Controller";
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dc->desc = "ASPEED 2700 INTC Controller";
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aic->num_lines = 32;
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aic->num_lines = 32;
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aic->num_ints = 9;
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aic->num_ints = 9;
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aic->mem_size = 0x4000;
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}
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}
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static const TypeInfo aspeed_2700_intc_info = {
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static const TypeInfo aspeed_2700_intc_info = {
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@ -25,6 +25,8 @@ struct AspeedINTCState {
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/*< public >*/
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/*< public >*/
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MemoryRegion iomem;
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MemoryRegion iomem;
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MemoryRegion iomem_container;
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uint32_t regs[ASPEED_INTC_NR_REGS];
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uint32_t regs[ASPEED_INTC_NR_REGS];
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OrIRQState orgates[ASPEED_INTC_NR_INTS];
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OrIRQState orgates[ASPEED_INTC_NR_INTS];
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qemu_irq output_pins[ASPEED_INTC_NR_INTS];
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qemu_irq output_pins[ASPEED_INTC_NR_INTS];
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@ -39,6 +41,7 @@ struct AspeedINTCClass {
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uint32_t num_lines;
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uint32_t num_lines;
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uint32_t num_ints;
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uint32_t num_ints;
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uint64_t mem_size;
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};
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};
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#endif /* ASPEED_INTC_H */
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#endif /* ASPEED_INTC_H */
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