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Preliminiary MIPS64 support, disabled by default due to performance impact.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2006-12-21 01:19:56 +00:00
parent 328a42406d
commit c570fd169c
12 changed files with 989 additions and 240 deletions
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67
target-mips/op_mem.c
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@ -75,6 +75,7 @@ void glue(op_sw, MEMSUFFIX) (void)
/* "half" load and stores. We must do the memory access inline,
or fault handling won't work. */
/* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */
void glue(op_lwl, MEMSUFFIX) (void)
{
uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
@ -125,6 +126,72 @@ void glue(op_sc, MEMSUFFIX) (void)
RETURN();
}
#ifdef MIPS_HAS_MIPS64
void glue(op_ld, MEMSUFFIX) (void)
{
T0 = glue(ldq, MEMSUFFIX)(T0);
RETURN();
}
void glue(op_sd, MEMSUFFIX) (void)
{
glue(stq, MEMSUFFIX)(T0, T1);
RETURN();
}
/* "half" load and stores. We must do the memory access inline,
or fault handling won't work. */
void glue(op_ldl, MEMSUFFIX) (void)
{
target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp);
RETURN();
}
void glue(op_ldr, MEMSUFFIX) (void)
{
target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp);
RETURN();
}
void glue(op_sdl, MEMSUFFIX) (void)
{
target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp);
glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
RETURN();
}
void glue(op_sdr, MEMSUFFIX) (void)
{
target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp);
glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
RETURN();
}
void glue(op_lld, MEMSUFFIX) (void)
{
T1 = T0;
T0 = glue(ldq, MEMSUFFIX)(T0);
env->CP0_LLAddr = T1;
RETURN();
}
void glue(op_scd, MEMSUFFIX) (void)
{
CALL_FROM_TB0(dump_sc);
if (T0 == env->CP0_LLAddr) {
glue(stq, MEMSUFFIX)(T0, T1);
T0 = 1;
} else {
T0 = 0;
}
RETURN();
}
#endif /* MIPS_HAS_MIPS64 */
#ifdef MIPS_USES_FPU
void glue(op_lwc1, MEMSUFFIX) (void)
{