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Preliminiary MIPS64 support, disabled by default due to performance impact.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2006-12-21 01:19:56 +00:00
parent 328a42406d
commit c570fd169c
12 changed files with 989 additions and 240 deletions
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29
target-mips/cpu.h
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@ -15,6 +15,16 @@ typedef unsigned char uint_fast8_t;
typedef unsigned int uint_fast16_t;
#endif
#ifdef MIPS_HAS_MIPS64
#define SIGN_EXTEND32(val) (((((uint64_t)(val)) & 0xFFFFFFFF) ^ 0x80000000) - 0x80000000)
/* target_ulong size spec */
#define TLSZ "%016llx"
#else
#define SIGN_EXTEND32(val) (val)
/* target_ulong size spec */
#define TLSZ "%08x"
#endif
typedef union fpr_t fpr_t;
union fpr_t {
float64 fd; /* ieee double precision */
@ -55,7 +65,12 @@ struct CPUMIPSState {
target_ulong gpr[32];
/* Special registers */
target_ulong PC;
uint32_t HI, LO;
#if TARGET_LONG_BITS > HOST_LONG_BITS
target_ulong t0;
target_ulong t1;
target_ulong t2;
#endif
target_ulong HI, LO;
uint32_t DCR; /* ? */
#if defined(MIPS_USES_FPU)
/* Floating point registers */
@ -106,7 +121,7 @@ struct CPUMIPSState {
uint32_t CP0_PageGrain;
uint32_t CP0_Wired;
uint32_t CP0_HWREna;
uint32_t CP0_BadVAddr;
target_ulong CP0_BadVAddr;
uint32_t CP0_Count;
uint64_t CP0_EntryHi;
uint32_t CP0_Compare;
@ -145,9 +160,9 @@ struct CPUMIPSState {
#define CP0Ca_WP 22
#define CP0Ca_IP 8
#define CP0Ca_EC 2
uint32_t CP0_EPC;
target_ulong CP0_EPC;
uint32_t CP0_PRid;
uint32_t CP0_EBase;
target_ulong CP0_EBase;
uint32_t CP0_Config0;
#define CP0C0_M 31
#define CP0C0_K23 28
@ -197,7 +212,7 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
uint32_t CP0_LLAddr;
target_ulong CP0_LLAddr;
uint32_t CP0_WatchLo;
uint32_t CP0_WatchHi;
uint32_t CP0_XContext;
@ -221,13 +236,13 @@ struct CPUMIPSState {
#define CP0DB_DDBL 2
#define CP0DB_DBp 1
#define CP0DB_DSS 0
uint32_t CP0_DEPC;
target_ulong CP0_DEPC;
uint32_t CP0_Performance0;
uint32_t CP0_TagLo;
uint32_t CP0_DataLo;
uint32_t CP0_TagHi;
uint32_t CP0_DataHi;
uint32_t CP0_ErrorEPC;
target_ulong CP0_ErrorEPC;
uint32_t CP0_DESAVE;
/* Qemu */
int interrupt_request;