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hw: Model ASPEED's Hash and Crypto Engine

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The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
SHA2, RSA and other cryptographic algorithms.

This initial model implements a subset of the device's functionality;
currently only MD5/SHA hashing, and on the ast2600's scatter gather
engine.

Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
[ clg: - fixes for 32-bit and OSX builds ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210409000253.1475587-2-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Joel Stanley 2021-05-01 10:03:51 +02:00 • committed by Cédric Le Goater
parent e9c568dbc2
commit c5475b3f9a
4 changed files with 434 additions and 0 deletions
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43
include/hw/misc/aspeed_hace.h Normal file
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/*
* ASPEED Hash and Crypto Engine
*
* Copyright (C) 2021 IBM Corp.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_HACE_H
#define ASPEED_HACE_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_HACE "aspeed.hace"
#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
#define ASPEED_HACE_NR_REGS (0x64 >> 2)
struct AspeedHACEState {
SysBusDevice parent;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[ASPEED_HACE_NR_REGS];
MemoryRegion *dram_mr;
AddressSpace dram_as;
};
struct AspeedHACEClass {
SysBusDeviceClass parent_class;
uint32_t src_mask;
uint32_t dest_mask;
uint32_t hash_mask;
};
#endif /* _ASPEED_HACE_H_ */