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target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations

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Add gvec helpers for doing Neon-style indexed non-fused fp
multiply-and-accumulate operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200828183354.27913-44-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-28 19:33:52 +01:00
parent d7ce81e553
commit c50d8d1440
2 changed files with 32 additions and 5 deletions
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10
target/arm/helper.h
View file

@ -740,6 +740,16 @@ DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,

27
target/arm/vec_helper.c
View file

@ -1085,7 +1085,7 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
#undef DO_MLA_IDX #undef DO_MLA_IDX
#define DO_FMUL_IDX(NAME, TYPE, H) \ #define DO_FMUL_IDX(NAME, ADD, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
{ \ { \
intptr_t i, j, oprsz = simd_oprsz(desc); \ intptr_t i, j, oprsz = simd_oprsz(desc); \
@ -1095,16 +1095,33 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
TYPE mm = m[H(i + idx)]; \ TYPE mm = m[H(i + idx)]; \
for (j = 0; j < segment; j++) { \ for (j = 0; j < segment; j++) { \
d[i + j] = TYPE##_mul(n[i + j], mm, stat); \ d[i + j] = TYPE##_##ADD(d[i + j], \
TYPE##_mul(n[i + j], mm, stat), stat); \
} \ } \
} \ } \
clear_tail(d, oprsz, simd_maxsz(desc)); \ clear_tail(d, oprsz, simd_maxsz(desc)); \
} }
DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2) #define float16_nop(N, M, S) (M)
DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4) #define float32_nop(N, M, S) (M)
DO_FMUL_IDX(gvec_fmul_idx_d, float64, ) #define float64_nop(N, M, S) (M)
DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16, H2)
DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32, H4)
DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64, )
/*
* Non-fused multiply-accumulate operations, for Neon. NB that unlike
* the fused ops below they assume accumulate both from and into Vd.
*/
DO_FMUL_IDX(gvec_fmla_nf_idx_h, add, float16, H2)
DO_FMUL_IDX(gvec_fmla_nf_idx_s, add, float32, H4)
DO_FMUL_IDX(gvec_fmls_nf_idx_h, sub, float16, H2)
DO_FMUL_IDX(gvec_fmls_nf_idx_s, sub, float32, H4)
#undef float16_nop
#undef float32_nop
#undef float64_nop
#undef DO_FMUL_IDX #undef DO_FMUL_IDX
#define DO_FMLA_IDX(NAME, TYPE, H) \ #define DO_FMLA_IDX(NAME, TYPE, H) \