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target-arm queue:

Browse source 
* Some of the preliminary patches for Cortex-A710 support
  * i.MX7 and i.MX6UL refactoring
  * Implement SRC device for i.MX7
  * Catch illegal-exception-return from EL3 with bad NSE/NS
  * Use 64-bit offsets for holding time_t differences in RTC devices
  * Model correct number of MPU regions for an505, an521, an524 boards
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTwbukZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ihBD/wK8Iz0KpTAwZBDAodnSZrh
 tQnJAvYFp8CxA4O8sZ9IeWsZh90gzsTCZi0NqUTTzvWCJfxkB7qTPdlJT5IzVxou
 oEUk2aogSJhRA3XRJzqArXsPlnZGSYDbtwKx4VtfCvOCCH08Y7nhnFaRj1oFnR4Q
 0PE/8YtGXTBxLHrO8U3tomg7zElzOUP8ZVZtb30BOyw1jtfSD03IZR8dzpA43u1E
 Hh418WvVekmwFoFNh8yUeHzbyXMZufzvbJPuDGJ8pPWwIpvSG6chOnKF8jZll+Ur
 DqOsDkGlQgcBR2QwYfSPClrEkX8yahJ95PBfM6giG+DQC7OiElqXqTiUGZcpgUVo
 uSUbzS4YPsxCnyVV6SBXV+f/8hdXBxOSHTgl7OAFa8X9OwWwspxHJ/v2o/2ibnUT
 hTTkFp/w1nQwVEN8xf1DOUpm/J2Wr8UeH4f776daSrfKAol2BKbHb8dOgGLQCwqb
 G+iDcE4bkzRqly6f+uVk8xSEZDd9P1NYoxKV+gNlV1dTspdHVpTC+rXMa8dRw5hI
 4KgaAslj++Xa229xkjORXCJ1cICRIebYg7+SjvTtGBYsFV7plsCcYb/R9yLmhVCf
 fKHKKaYe9sQJ82apOIkTc+nnW8BQQx6XUmU/A//iZ8JGLk6DpJcZ8f1m/2rVZTsl
 9+lsmpBf4w+uR4o+Womhfw==
 =MFh3
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20230831' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTwbukZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ihBD/wK8Iz0KpTAwZBDAodnSZrh
# tQnJAvYFp8CxA4O8sZ9IeWsZh90gzsTCZi0NqUTTzvWCJfxkB7qTPdlJT5IzVxou
# oEUk2aogSJhRA3XRJzqArXsPlnZGSYDbtwKx4VtfCvOCCH08Y7nhnFaRj1oFnR4Q
# 0PE/8YtGXTBxLHrO8U3tomg7zElzOUP8ZVZtb30BOyw1jtfSD03IZR8dzpA43u1E
# Hh418WvVekmwFoFNh8yUeHzbyXMZufzvbJPuDGJ8pPWwIpvSG6chOnKF8jZll+Ur
# DqOsDkGlQgcBR2QwYfSPClrEkX8yahJ95PBfM6giG+DQC7OiElqXqTiUGZcpgUVo
# uSUbzS4YPsxCnyVV6SBXV+f/8hdXBxOSHTgl7OAFa8X9OwWwspxHJ/v2o/2ibnUT
# hTTkFp/w1nQwVEN8xf1DOUpm/J2Wr8UeH4f776daSrfKAol2BKbHb8dOgGLQCwqb
# G+iDcE4bkzRqly6f+uVk8xSEZDd9P1NYoxKV+gNlV1dTspdHVpTC+rXMa8dRw5hI
# 4KgaAslj++Xa229xkjORXCJ1cICRIebYg7+SjvTtGBYsFV7plsCcYb/R9yLmhVCf
# fKHKKaYe9sQJ82apOIkTc+nnW8BQQx6XUmU/A//iZ8JGLk6DpJcZ8f1m/2rVZTsl
# 9+lsmpBf4w+uR4o+Womhfw==
# =MFh3
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 31 Aug 2023 06:43:53 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230831' of https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)
  hw/arm: Set number of MPU regions correctly for an505, an521, an524
  hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
  target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
  rtc: Use time_t for passing and returning time offsets
  hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
  hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
  hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
  target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
  Add i.MX7 SRC device implementation
  Add i.MX7 missing TZ devices and memory regions
  Refactor i.MX7 processor code
  Add i.MX6UL missing devices.
  Refactor i.MX6UL processor code
  Remove i.MX7 IOMUX GPR device from i.MX6UL
  target/arm: properly document FEAT_CRC32
  target/arm: Implement FEAT_HPDS2 as a no-op
  target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
  target/arm: Apply access checks to neoverse-v1 special registers
  target/arm: Apply access checks to neoverse-n1 special registers
  target/arm: Introduce make_ccsidr64
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-08-31 08:31:03 -04:00
commit c4e5f9a29f
31 changed files with 1393 additions and 372 deletions
Download patch file Download diff file Expand all files Collapse all files

16
hw/arm/armsse.c
View file

@ -85,6 +85,8 @@ static Property iotkit_properties[] = {
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
DEFINE_PROP_END_OF_LIST()
};
@ -98,6 +100,10 @@ static Property sse200_properties[] = {
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
DEFINE_PROP_END_OF_LIST()
};
@ -109,6 +115,8 @@ static Property sse300_properties[] = {
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
DEFINE_PROP_END_OF_LIST()
};
@ -1029,6 +1037,14 @@ static void armsse_realize(DeviceState *dev, Error **errp)
return;
}
}
if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
s->cpu_mpu_ns[i], errp)) {
return;
}
if (!object_property_set_uint(cpuobj, "mpu-s-regions",
s->cpu_mpu_s[i], errp)) {
return;
}
if (i > 0) {
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,

21
hw/arm/armv7m.c
View file

@ -334,6 +334,25 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
}
/*
* Real M-profile hardware can be configured with a different number of
* MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
* support that yet, so catch attempts to select that.
*/
if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
s->mpu_ns_regions != s->mpu_s_regions) {
error_setg(errp,
"mpu-ns-regions and mpu-s-regions properties must have the same value");
return;
}
if (s->mpu_ns_regions != UINT_MAX &&
object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
s->mpu_ns_regions, errp)) {
return;
}
}
/*
* Tell the CPU where the NVIC is; it will fail realize if it doesn't
* have one. Similarly, tell the NVIC where its CPU is.
@ -530,6 +549,8 @@ static Property armv7m_properties[] = {
false),
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
DEFINE_PROP_END_OF_LIST(),
};

174
hw/arm/fsl-imx6ul.c
View file

@ -64,12 +64,7 @@ static void fsl_imx6ul_init(Object *obj)
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* GPR
*/
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
/*
* GPIOs 1 to 5
* GPIOs
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
@ -77,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* GPT 1, 2
* GPTs
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
@ -85,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* EPIT 1, 2
* EPITs
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
@ -93,7 +88,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* eCSPI
* eCSPIs
*/
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
@ -101,7 +96,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* I2C
* I2Cs
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@ -109,7 +104,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* UART
* UARTs
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
@ -117,25 +112,31 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* Ethernet
* Ethernets
*/
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
}
/* USB */
/*
* USB PHYs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
snprintf(name, NAME_SIZE, "usbphy%d", i);
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
}
/*
* USBs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
/*
* SDHCI
* SDHCIs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
@ -143,7 +144,7 @@ static void fsl_imx6ul_init(Object *obj)
}
/*
* Watchdog
* Watchdogs
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
@ -189,10 +190,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
* A7MPCORE DAP
*/
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
0x100000);
FSL_IMX6UL_A7MPCORE_DAP_SIZE);
/*
* GPT 1, 2
* GPTs
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@ -217,7 +218,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* EPIT 1, 2
* EPITs
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@ -242,7 +243,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* GPIO
* GPIOs
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@ -284,17 +285,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* IOMUXC and IOMUXC_GPR
* IOMUXC
*/
for (i = 0; i < 1; i++) {
static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
FSL_IMX6UL_IOMUXC_ADDR,
FSL_IMX6UL_IOMUXC_GPR_ADDR,
};
snprintf(name, NAME_SIZE, "iomuxc%d", i);
create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
}
create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
FSL_IMX6UL_IOMUXC_SIZE);
create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
FSL_IMX6UL_IOMUXC_GPR_SIZE);
/*
* CCM
@ -314,7 +310,9 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
/* Initialize all ECSPI */
/*
* ECSPIs
*/
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
FSL_IMX6UL_ECSPI1_ADDR,
@ -342,7 +340,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* I2C
* I2Cs
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@ -368,7 +366,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* UART
* UARTs
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@ -406,7 +404,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
}
/*
* Ethernet
* Ethernets
*
* We must use two loops since phy_connected affects the other interface
* and we have to set all properties before calling sysbus_realize().
@ -459,28 +457,45 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
}
/* USB */
/*
* USB PHYs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
static const hwaddr
FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
FSL_IMX6UL_USBPHY1_ADDR,
FSL_IMX6UL_USBPHY2_ADDR,
};
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
FSL_IMX6UL_USB_PHYn_ADDR[i]);
}
/*
* USBs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
FSL_IMX6UL_USBO2_USB1_ADDR,
FSL_IMX6UL_USBO2_USB2_ADDR,
};
static const int FSL_IMX6UL_USBn_IRQ[] = {
FSL_IMX6UL_USB1_IRQ,
FSL_IMX6UL_USB2_IRQ,
};
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
FSL_IMX6UL_USB02_USBn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_USBn_IRQ[i]));
}
/*
* USDHC
* USDHCs
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@ -512,7 +527,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
/*
* Watchdog
* Watchdogs
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@ -520,6 +535,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_WDOG2_ADDR,
FSL_IMX6UL_WDOG3_ADDR,
};
static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
FSL_IMX6UL_WDOG1_IRQ,
FSL_IMX6UL_WDOG2_IRQ,
@ -537,42 +553,66 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_WDOGn_IRQ[i]));
}
/*
* GPR
*/
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
/*
* SDMA
*/
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
FSL_IMX6UL_SDMA_SIZE);
/*
* SAI (Audio SSI (Synchronous Serial Interface))
* SAIs (Audio SSI (Synchronous Serial Interface))
*/
create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
FSL_IMX6UL_SAI1_ADDR,
FSL_IMX6UL_SAI2_ADDR,
FSL_IMX6UL_SAI3_ADDR,
};
snprintf(name, NAME_SIZE, "sai%d", i);
create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
FSL_IMX6UL_SAIn_SIZE);
}
/*
* PWM
* PWMs
*/
create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
FSL_IMX6UL_PWM1_ADDR,
FSL_IMX6UL_PWM2_ADDR,
FSL_IMX6UL_PWM3_ADDR,
FSL_IMX6UL_PWM4_ADDR,
FSL_IMX6UL_PWM5_ADDR,
FSL_IMX6UL_PWM6_ADDR,
FSL_IMX6UL_PWM7_ADDR,
FSL_IMX6UL_PWM8_ADDR,
};
snprintf(name, NAME_SIZE, "pwm%d", i);
create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
FSL_IMX6UL_PWMn_SIZE);
}
/*
* Audio ASRC (asynchronous sample rate converter)
*/
create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
FSL_IMX6UL_ASRC_SIZE);
/*
* CAN
* CANs
*/
create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
FSL_IMX6UL_CAN1_ADDR,
FSL_IMX6UL_CAN2_ADDR,
};
snprintf(name, NAME_SIZE, "can%d", i);
create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
FSL_IMX6UL_CANn_SIZE);
}
/*
* APHB_DMA
@ -590,13 +630,27 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
};
snprintf(name, NAME_SIZE, "adc%d", i);
create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
FSL_IMX6UL_ADCn_SIZE);
}
/*
* LCD
*/
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
FSL_IMX6UL_LCDIF_SIZE);
/*
* CSU
*/
create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
FSL_IMX6UL_CSU_SIZE);
/*
* TZASC
*/
create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
FSL_IMX6UL_TZASC_SIZE);
/*
* ROM memory

201
hw/arm/fsl-imx7.c
View file

@ -36,6 +36,9 @@ static void fsl_imx7_init(Object *obj)
char name[NAME_SIZE];
int i;
/*
* CPUs
*/
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i],
@ -49,7 +52,7 @@ static void fsl_imx7_init(Object *obj)
TYPE_A15MPCORE_PRIV);
/*
* GPIOs 1 to 7
* GPIOs
*/
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
@ -57,7 +60,7 @@ static void fsl_imx7_init(Object *obj)
}
/*
* GPT1, 2, 3, 4
* GPTs
*/
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
@ -79,19 +82,29 @@ static void fsl_imx7_init(Object *obj)
*/
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
/*
* SRC
*/
object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
/*
* ECSPIs
*/
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
/*
* I2Cs
*/
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
/*
* UART
* UARTs
*/
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
@ -99,7 +112,7 @@ static void fsl_imx7_init(Object *obj)
}
/*
* Ethernet
* Ethernets
*/
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
@ -107,7 +120,7 @@ static void fsl_imx7_init(Object *obj)
}
/*
* SDHCI
* SDHCIs
*/
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
@ -120,7 +133,7 @@ static void fsl_imx7_init(Object *obj)
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* Watchdog
* Watchdogs
*/
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
@ -132,8 +145,14 @@ static void fsl_imx7_init(Object *obj)
*/
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
/*
* PCIE
*/
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
/*
* USBs
*/
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@ -156,6 +175,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
return;
}
/*
* CPUs
*/
for (i = 0; i < smp_cpus; i++) {
o = OBJECT(&s->cpu[i]);
@ -206,10 +228,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
* A7MPCORE DAP
*/
create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
0x100000);
FSL_IMX7_A7MPCORE_DAP_SIZE);
/*
* GPT1, 2, 3, 4
* GPTs
*/
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@ -234,6 +256,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_GPTn_IRQ[i]));
}
/*
* GPIOs
*/
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
FSL_IMX7_GPIO1_ADDR,
@ -281,16 +306,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
/*
* IOMUXC and IOMUXC_LPSR
*/
for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
FSL_IMX7_IOMUXC_ADDR,
FSL_IMX7_IOMUXC_LPSR_ADDR,
};
snprintf(name, NAME_SIZE, "iomuxc%d", i);
create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
FSL_IMX7_IOMUXCn_SIZE);
}
create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
FSL_IMX7_IOMUXC_SIZE);
create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
FSL_IMX7_IOMUXC_LPSR_SIZE);
/*
* CCM
@ -310,7 +329,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
/* Initialize all ECSPI */
/*
* ECSPIs
*/
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
FSL_IMX7_ECSPI1_ADDR,
@ -335,6 +356,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_SPIn_IRQ[i]));
}
/*
* I2Cs
*/
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
FSL_IMX7_I2C1_ADDR,
@ -359,7 +383,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
}
/*
* UART
* UARTs
*/
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@ -394,7 +418,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
}
/*
* Ethernet
* Ethernets
*
* We must use two loops since phy_connected affects the other interface
* and we have to set all properties before calling sysbus_realize().
@ -434,7 +458,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
}
/*
* USDHC
* USDHCs
*/
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@ -464,15 +488,16 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
* SNVS
*/
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
/*
* SRC
*/
create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
/*
* Watchdog
* Watchdogs
*/
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@ -509,25 +534,49 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
/*
* PWM
* PWMs
*/
create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
FSL_IMX7_PWM1_ADDR,
FSL_IMX7_PWM2_ADDR,
FSL_IMX7_PWM3_ADDR,
FSL_IMX7_PWM4_ADDR,
};
snprintf(name, NAME_SIZE, "pwm%d", i);
create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
FSL_IMX7_PWMn_SIZE);
}
/*
* CAN
* CANs
*/
create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
FSL_IMX7_CAN1_ADDR,
FSL_IMX7_CAN2_ADDR,
};
snprintf(name, NAME_SIZE, "can%d", i);
create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
FSL_IMX7_CANn_SIZE);
}
/*
* SAI (Audio SSI (Synchronous Serial Interface))
* SAIs (Audio SSI (Synchronous Serial Interface))
*/
create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
FSL_IMX7_SAI1_ADDR,
FSL_IMX7_SAI2_ADDR,
FSL_IMX7_SAI3_ADDR,
};
snprintf(name, NAME_SIZE, "sai%d", i);
create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
FSL_IMX7_SAIn_SIZE);
}
/*
* OCOTP
@ -535,9 +584,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
FSL_IMX7_OCOTP_SIZE);
/*
* GPR
*/
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
/*
* PCIE
*/
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
@ -550,7 +605,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
/*
* USBs
*/
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
FSL_IMX7_USBMISC1_ADDR,
@ -612,6 +669,70 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
*/
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
FSL_IMX7_PCIE_PHY_SIZE);
/*
* CSU
*/
create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
FSL_IMX7_CSU_SIZE);
/*
* TZASC
*/
create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
FSL_IMX7_TZASC_SIZE);
/*
* OCRAM memory
*/
memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
FSL_IMX7_OCRAM_MEM_SIZE,
&error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
&s->ocram);
/*
* OCRAM EPDC memory
*/
memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
FSL_IMX7_OCRAM_EPDC_SIZE,
&error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
&s->ocram_epdc);
/*
* OCRAM PXP memory
*/
memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
FSL_IMX7_OCRAM_PXP_SIZE,
&error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
&s->ocram_pxp);
/*
* OCRAM_S memory
*/
memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
FSL_IMX7_OCRAM_S_SIZE,
&error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
&s->ocram_s);
/*
* ROM memory
*/
memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
FSL_IMX7_ROM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
&s->rom);
/*
* CAAM memory
*/
memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
&s->caam);
}
static Property fsl_imx7_properties[] = {

29
hw/arm/mps2-tz.c
View file

@ -124,6 +124,10 @@ struct MPS2TZMachineClass {
int uart_overflow_irq; /* number of the combined UART overflow IRQ */
uint32_t init_svtor; /* init-svtor setting for SSE */
uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
const RAMInfo *raminfo;
const char *armsse_type;
uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@ -183,6 +187,9 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
#define MPS3_DDR_SIZE (2 * GiB)
#endif
/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
#define MPU_REGION_DEFAULT UINT32_MAX
static const uint32_t an505_oscclk[] = {
40000000,
24580000,
@ -828,6 +835,20 @@ static void mps2tz_common_init(MachineState *machine)
OBJECT(system_memory), &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
}
if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
}
if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
}
if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
}
}
qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@ -1256,10 +1277,17 @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
mc->init = mps2tz_common_init;
mc->reset = mps2_machine_reset;
iic->check = mps2_tz_idau_check;
/* Most machines leave these at the SSE defaults */
mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
}
static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@ -1396,6 +1424,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
mmc->numirq = 96;
mmc->uart_overflow_irq = 48;
mmc->init_svtor = 0x00000000;
mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
mmc->sram_addr_width = 21;
mmc->raminfo = an547_raminfo;
mmc->armsse_type = TYPE_SSE300;