motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Preliminary textra trigger CSR writting support

Browse source 
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to
zero for now.

For textra.MHSELECT field, the only legal values are 0 (ignore) and 4
(mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and
writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is
aligned to RISC-V SPIKE simulator.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240826024657.262553-2-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alvin Chang 2024-08-26 10:46:56 +08:00 • committed by Alistair Francis
parent c5757f808b
commit c4db48cc24
2 changed files with 73 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

10
target/riscv/cpu_bits.h
View file

@ -947,6 +947,16 @@ typedef enum RISCVException {
#define JVT_BASE (~0x3F)
/* Debug Sdtrig CSR masks */
#define TEXTRA32_MHVALUE 0xFC000000
#define TEXTRA32_MHSELECT 0x03800000
#define TEXTRA32_SBYTEMASK 0x000C0000
#define TEXTRA32_SVALUE 0x0003FFFC
#define TEXTRA32_SSELECT 0x00000003
#define TEXTRA64_MHVALUE 0xFFF8000000000000ULL
#define TEXTRA64_MHSELECT 0x0007000000000000ULL
#define TEXTRA64_SBYTEMASK 0x000000F000000000ULL
#define TEXTRA64_SVALUE 0x00000003FFFFFFFCULL
#define TEXTRA64_SSELECT 0x0000000000000003ULL
#define MCONTEXT32 0x0000003F
#define MCONTEXT64 0x0000000000001FFFULL
#define MCONTEXT32_HCONTEXT 0x0000007F