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rust: pl011: remove duplicate definitions

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Unify the "Interrupt" enum and the "INT_*" constants with a struct
that contains the bits.  The "int_level" and "int_enabled" fields
could use a crate such as "bitflags".

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-12-02 17:28:26 +01:00
parent a1ab4eed8d
commit c44818a5fd
2 changed files with 29 additions and 49 deletions
Download patch file Download diff file Expand all files Collapse all files

32
rust/hw/char/pl011/src/device.rs
View file

@ -191,7 +191,7 @@ impl PL011Registers {
self.flags.set_receive_fifo_empty(true);
}
if self.read_count + 1 == self.read_trigger {
self.int_level &= !registers::INT_RX;
self.int_level &= !Interrupt::RX.0;
}
// Update error bits.
self.receive_status_error_clear.set_from_data(c);
@ -230,7 +230,7 @@ impl PL011Registers {
DR => {
// interrupts always checked
let _ = self.loopback_tx(value);
self.int_level |= registers::INT_TX;
self.int_level |= Interrupt::TX.0;
return true;
}
RSR => {
@ -354,19 +354,19 @@ impl PL011Registers {
// Change interrupts based on updated FR
let mut il = self.int_level;
il &= !Interrupt::MS;
il &= !Interrupt::MS.0;
if self.flags.data_set_ready() {
il |= Interrupt::DSR as u32;
il |= Interrupt::DSR.0;
}
if self.flags.data_carrier_detect() {
il |= Interrupt::DCD as u32;
il |= Interrupt::DCD.0;
}
if self.flags.clear_to_send() {
il |= Interrupt::CTS as u32;
il |= Interrupt::CTS.0;
}
if self.flags.ring_indicator() {
il |= Interrupt::RI as u32;
il |= Interrupt::RI.0;
}
self.int_level = il;
true
@ -444,7 +444,7 @@ impl PL011Registers {
}
if self.read_count == self.read_trigger {
self.int_level |= registers::INT_RX;
self.int_level |= Interrupt::RX.0;
return true;
}
false
@ -651,16 +651,12 @@ impl PL011State {
/// Which bits in the interrupt status matter for each outbound IRQ line ?
const IRQMASK: [u32; 6] = [
/* combined IRQ */
Interrupt::E
| Interrupt::MS
| Interrupt::RT as u32
| Interrupt::TX as u32
| Interrupt::RX as u32,
Interrupt::RX as u32,
Interrupt::TX as u32,
Interrupt::RT as u32,
Interrupt::MS,
Interrupt::E,
Interrupt::E.0 | Interrupt::MS.0 | Interrupt::RT.0 | Interrupt::TX.0 | Interrupt::RX.0,
Interrupt::RX.0,
Interrupt::TX.0,
Interrupt::RT.0,
Interrupt::MS.0,
Interrupt::E.0,
];
/// # Safety

46
rust/hw/char/pl011/src/lib.rs
View file

@ -100,7 +100,6 @@ enum RegisterOffset {
//Reserved = 0x04C,
}
#[allow(dead_code)]
mod registers {
//! Device registers exposed as typed structs which are backed by arbitrary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
@ -521,38 +520,23 @@ mod registers {
}
/// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
pub const INT_OE: u32 = 1 << 10;
pub const INT_BE: u32 = 1 << 9;
pub const INT_PE: u32 = 1 << 8;
pub const INT_FE: u32 = 1 << 7;
pub const INT_RT: u32 = 1 << 6;
pub const INT_TX: u32 = 1 << 5;
pub const INT_RX: u32 = 1 << 4;
pub const INT_DSR: u32 = 1 << 3;
pub const INT_DCD: u32 = 1 << 2;
pub const INT_CTS: u32 = 1 << 1;
pub const INT_RI: u32 = 1 << 0;
pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
#[repr(u32)]
pub enum Interrupt {
OE = 1 << 10,
BE = 1 << 9,
PE = 1 << 8,
FE = 1 << 7,
RT = 1 << 6,
TX = 1 << 5,
RX = 1 << 4,
DSR = 1 << 3,
DCD = 1 << 2,
CTS = 1 << 1,
RI = 1 << 0,
}
pub struct Interrupt(pub u32);
impl Interrupt {
pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
pub const OE: Self = Self(1 << 10);
pub const BE: Self = Self(1 << 9);
pub const PE: Self = Self(1 << 8);
pub const FE: Self = Self(1 << 7);
pub const RT: Self = Self(1 << 6);
pub const TX: Self = Self(1 << 5);
pub const RX: Self = Self(1 << 4);
pub const DSR: Self = Self(1 << 3);
pub const DCD: Self = Self(1 << 2);
pub const CTS: Self = Self(1 << 1);
pub const RI: Self = Self(1 << 0);
pub const E: Self = Self(Self::OE.0 | Self::BE.0 | Self::PE.0 | Self::FE.0);
pub const MS: Self = Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0 | Self::CTS.0);
}
}