motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-08 10:13:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-arm: Drop success/fail return from cpreg read and write functions

Browse source 
All cpreg read and write functions now return 0, so we can clean up
their prototypes:
 * write functions return void
 * read functions return the value rather than taking a pointer
   to write the value to

This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
This commit is contained in:
Peter Maydell 2014-02-20 10:35:54 +00:00
parent 92611c0019
commit c4241c7d38
6 changed files with 154 additions and 238 deletions
Download patch file Download diff file Expand all files Collapse all files

36
hw/arm/pxa2xx.c
View file

@ -224,27 +224,24 @@ static const VMStateDescription vmstate_pxa2xx_cm = {
}
};
static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
*value = s->clkcfg;
return 0;
return s->clkcfg;
}
static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->clkcfg = value & 0xf;
if (value & 2) {
printf("%s: CPU frequency change attempt\n", __func__);
}
return 0;
}
static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = {
@ -310,36 +307,29 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]);
}
return 0;
}
static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
*value = s->pmnc;
return 0;
return s->pmnc;
}
static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->pmnc = value;
return 0;
}
static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
if (s->pmnc & 1) {
*value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
} else {
*value = 0;
return 0;
}
return 0;
}
static const ARMCPRegInfo pxa_cp_reginfo[] = {

11
hw/arm/pxa2xx_pic.c
View file

@ -217,20 +217,17 @@ static const int pxa2xx_cp_reg_map[0x10] = {
[0xa] = ICPR2,
};
static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
int offset = pxa2xx_cp_reg_map[ri->crn];
*value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
return 0;
return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
}
static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int offset = pxa2xx_cp_reg_map[ri->crn];
pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
return 0;
}
#define REGINFO_FOR_PIC_CP(NAME, CRN) \