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target/riscv: add ssstateen

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ssstateen is defined in RVA22 as:

"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."

Add ssstateen as a named feature that is available if we also have
smstateen.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-11-13 14:17:48 -03:00 • committed by Alistair Francis
parent 7e4f75cadf
commit c3de19c0cc
3 changed files with 11 additions and 1 deletions
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2
target/riscv/cpu.c
View file

@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@ -1677,6 +1678,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
*/
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
DEFINE_PROP_END_OF_LIST(),
};

1
target/riscv/cpu_cfg.h
View file

@ -140,6 +140,7 @@ struct RISCVCPUConfig {
/* Named features */
bool ext_svade;
bool ext_zic64b;
bool ext_ssstateen;
/*
* Always 'true' booleans for named features

9
target/riscv/tcg/tcg-cpu.c
View file

@ -204,10 +204,15 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
* All other named features are already enabled
* in riscv_tcg_cpu_instance_init().
*/
if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
switch (feat_offset) {
case CPU_CFG_OFFSET(ext_zic64b):
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
break;
case CPU_CFG_OFFSET(ext_ssstateen):
cpu->cfg.ext_smstateen = true;
break;
}
}
@ -343,6 +348,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
cpu->cfg.cbop_blocksize == 64 &&
cpu->cfg.cboz_blocksize == 64;
cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
}
static void riscv_cpu_validate_g(RISCVCPU *cpu)