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cpu: Pass CPUState to cpu_interrupt()

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Move it to qom/cpu.h to avoid issues with include order.

Change pc_acpi_smi_interrupt() opaque to X86CPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-01-18 15:03:43 +01:00
parent d8ed887bdc
commit c3affe5670
37 changed files with 106 additions and 99 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/arm/omap1.c
View file

@ -1523,7 +1523,7 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
omap_clk clk;
if (value & (1 << 11)) { /* SETARM_IDLE */
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
}
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
@ -3759,7 +3759,7 @@ void omap_mpu_wakeup(void *opaque, int irq, int req)
CPUState *cpu = CPU(mpu->cpu);
if (cpu->halted) {
cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB);
cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}

5
hw/arm/pic_cpu.c
View file

@ -15,20 +15,19 @@
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
case ARM_PIC_CPU_FIQ:
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_FIQ);
cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
}

7
hw/arm/pxa2xx.c
View file

@ -263,14 +263,14 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
/* Fall through. */
case 2:
/* Deep-Idle */
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
@ -301,7 +301,8 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
#endif
/* Suspend */
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)),
CPU_INTERRUPT_HALT);
goto message;

2
hw/arm/pxa2xx_gpio.c
View file

@ -120,7 +120,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level)
/* Wake-up GPIOs */
if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}

6
hw/arm/pxa2xx_pic.c
View file

@ -52,7 +52,7 @@ static void pxa2xx_pic_update(void *opaque)
mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
if (mask[0] || mask[1]) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
@ -60,13 +60,13 @@ static void pxa2xx_pic_update(void *opaque)
mask[1] = s->int_pending[1] & s->int_enabled[1];
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
}
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
}