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aspeed queue:

Browse source 
* Update of buildroot images to 2023.11 (6.6.3 kernel)
 * Check of the valid CPU type supported by aspeed machines
 * Simplified models for the IBM's FSI bus and the Aspeed
   controller bridge
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Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging

aspeed queue:

* Update of buildroot images to 2023.11 (6.6.3 kernel)
* Check of the valid CPU type supported by aspeed machines
* Simplified models for the IBM's FSI bus and the Aspeed
  controller bridge

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# gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
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# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu:
  hw/fsi: Update MAINTAINER list
  hw/fsi: Added FSI documentation
  hw/fsi: Added qtest
  hw/arm: Hook up FSI module in AST2600
  hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
  hw/fsi: Introduce IBM's FSI master
  hw/fsi: Introduce IBM's cfam
  hw/fsi: Introduce IBM's fsi-slave model
  hw/fsi: Introduce IBM's FSI Bus
  hw/fsi: Introduce IBM's scratchpad device
  hw/fsi: Introduce IBM's Local bus
  hw/arm/aspeed: Check for CPU types in machine_run_board_init()
  hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
  hw/arm/aspeed: Init CPU defaults in a common helper
  hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
  hw/arm/aspeed: Remove dead code
  tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-02-01 14:42:11 +00:00
commit c3709fde59
30 changed files with 1578 additions and 58 deletions
Download patch file Download diff file Expand all files Collapse all files

18
tests/avocado/machine_aspeed.py
View file

@ -155,6 +155,7 @@ class AST2x00Machine(QemuSystemTest):
time.sleep(0.1)
exec_command(self, 'root')
time.sleep(0.1)
exec_command(self, "passw0rd")
def do_test_arm_aspeed_buildroot_poweroff(self):
exec_command_and_wait_for_pattern(self, 'poweroff',
@ -167,14 +168,14 @@ class AST2x00Machine(QemuSystemTest):
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
'images/ast2500-evb/buildroot-2023.11/flash.img')
image_hash = ('c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
self.do_test_arm_aspeed_buildroot_start(image_path, '0x0', 'Aspeed AST2500 EVB')
exec_command_and_wait_for_pattern(self,
'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@ -195,8 +196,8 @@ class AST2x00Machine(QemuSystemTest):
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
'images/ast2600-evb/buildroot-2023.11/flash.img')
image_hash = ('b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
@ -206,17 +207,17 @@ class AST2x00Machine(QemuSystemTest):
'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
self.vm.add_args('-device',
'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
exec_command_and_wait_for_pattern(self,
'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon0/temp1_input', '0')
'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
property='temperature', value=18000);
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon0/temp1_input', '18000')
'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
exec_command_and_wait_for_pattern(self,
'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
@ -261,7 +262,6 @@ class AST2x00Machine(QemuSystemTest):
self.vm.add_args('-device',
'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
exec_command(self, "passw0rd")
exec_command_and_wait_for_pattern(self,
'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',

205
tests/qtest/aspeed_fsi-test.c Normal file
View file

@ -0,0 +1,205 @@
/*
* QTest testcases for IBM's Flexible Service Interface (FSI)
*
* Copyright (c) 2023 IBM Corporation
*
* Authors:
* Ninad Palsule <ninad@linux.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include <glib/gstdio.h>
#include "qemu/module.h"
#include "libqtest-single.h"
/* Registers from ast2600 specifications */
#define ASPEED_FSI_ENGINER_TRIGGER 0x04
#define ASPEED_FSI_OPB0_BUS_SELECT 0x10
#define ASPEED_FSI_OPB1_BUS_SELECT 0x28
#define ASPEED_FSI_OPB0_RW_DIRECTION 0x14
#define ASPEED_FSI_OPB1_RW_DIRECTION 0x2c
#define ASPEED_FSI_OPB0_XFER_SIZE 0x18
#define ASPEED_FSI_OPB1_XFER_SIZE 0x30
#define ASPEED_FSI_OPB0_BUS_ADDR 0x1c
#define ASPEED_FSI_OPB1_BUS_ADDR 0x34
#define ASPEED_FSI_INTRRUPT_CLEAR 0x40
#define ASPEED_FSI_INTRRUPT_STATUS 0x48
#define ASPEED_FSI_OPB0_BUS_STATUS 0x80
#define ASPEED_FSI_OPB1_BUS_STATUS 0x8c
#define ASPEED_FSI_OPB0_READ_DATA 0x84
#define ASPEED_FSI_OPB1_READ_DATA 0x90
/*
* FSI Base addresses from the ast2600 specifications.
*/
#define AST2600_OPB_FSI0_BASE_ADDR 0x1e79b000
#define AST2600_OPB_FSI1_BASE_ADDR 0x1e79b100
static uint32_t aspeed_fsi_base_addr;
static uint32_t aspeed_fsi_readl(QTestState *s, uint32_t reg)
{
return qtest_readl(s, aspeed_fsi_base_addr + reg);
}
static void aspeed_fsi_writel(QTestState *s, uint32_t reg, uint32_t val)
{
qtest_writel(s, aspeed_fsi_base_addr + reg, val);
}
/* Setup base address and select register */
static void test_fsi_setup(QTestState *s, uint32_t base_addr)
{
uint32_t curval;
aspeed_fsi_base_addr = base_addr;
/* Set the base select register */
if (base_addr == AST2600_OPB_FSI0_BASE_ADDR) {
/* Unselect FSI1 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
g_assert_cmpuint(curval, ==, 0x0);
/* Select FSI0 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
g_assert_cmpuint(curval, ==, 0x1);
} else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) {
/* Unselect FSI0 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
g_assert_cmpuint(curval, ==, 0x0);
/* Select FSI1 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
g_assert_cmpuint(curval, ==, 0x1);
} else {
g_assert_not_reached();
}
}
static void test_fsi_reg_change(QTestState *s, uint32_t reg, uint32_t newval)
{
uint32_t base;
uint32_t curval;
base = aspeed_fsi_readl(s, reg);
aspeed_fsi_writel(s, reg, newval);
curval = aspeed_fsi_readl(s, reg);
g_assert_cmpuint(curval, ==, newval);
aspeed_fsi_writel(s, reg, base);
curval = aspeed_fsi_readl(s, reg);
g_assert_cmpuint(curval, ==, base);
}
static void test_fsi0_master_regs(const void *data)
{
QTestState *s = (QTestState *)data;
test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
test_fsi_reg_change(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0xF3F4F514);
test_fsi_reg_change(s, ASPEED_FSI_OPB0_XFER_SIZE, 0xF3F4F518);
test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xF3F4F51c);
test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_STATUS, 0xF3F4F580);
test_fsi_reg_change(s, ASPEED_FSI_OPB0_READ_DATA, 0xF3F4F584);
}
static void test_fsi1_master_regs(const void *data)
{
QTestState *s = (QTestState *)data;
test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
test_fsi_reg_change(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0xF3F4F514);
test_fsi_reg_change(s, ASPEED_FSI_OPB1_XFER_SIZE, 0xF3F4F518);
test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xF3F4F51c);
test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_STATUS, 0xF3F4F580);
test_fsi_reg_change(s, ASPEED_FSI_OPB1_READ_DATA, 0xF3F4F584);
}
static void test_fsi0_getcfam_addr0(const void *data)
{
QTestState *s = (QTestState *)data;
uint32_t curval;
test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
/* Master access direction read */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0x1);
/* word */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_XFER_SIZE, 0x3);
/* Address */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xa0000000);
aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
g_assert_cmpuint(curval, ==, 0x10000);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_STATUS);
g_assert_cmpuint(curval, ==, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_READ_DATA);
g_assert_cmpuint(curval, ==, 0x152d02c0);
}
static void test_fsi1_getcfam_addr0(const void *data)
{
QTestState *s = (QTestState *)data;
uint32_t curval;
test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
/* Master access direction read */
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0x1);
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_XFER_SIZE, 0x3);
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xa0000000);
aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
g_assert_cmpuint(curval, ==, 0x20000);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_STATUS);
g_assert_cmpuint(curval, ==, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_READ_DATA);
g_assert_cmpuint(curval, ==, 0x152d02c0);
}
int main(int argc, char **argv)
{
int ret = -1;
QTestState *s;
g_test_init(&argc, &argv, NULL);
s = qtest_init("-machine ast2600-evb ");
/* Tests for OPB/FSI0 */
qtest_add_data_func("/aspeed-fsi-test/test_fsi0_master_regs", s,
test_fsi0_master_regs);
qtest_add_data_func("/aspeed-fsi-test/test_fsi0_getcfam_addr0", s,
test_fsi0_getcfam_addr0);
/* Tests for OPB/FSI1 */
qtest_add_data_func("/aspeed-fsi-test/test_fsi1_master_regs", s,
test_fsi1_master_regs);
qtest_add_data_func("/aspeed-fsi-test/test_fsi1_getcfam_addr0", s,
test_fsi1_getcfam_addr0);
ret = g_test_run();
qtest_quit(s);
return ret;
}

1
tests/qtest/meson.build
View file

@ -217,6 +217,7 @@ qtests_arm = \
(config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
(config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
['arm-cpu-features',
'boot-serial-test']