mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 15:23:53 -06:00
aspeed queue:
* Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= =0C5S -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
c3709fde59
30 changed files with 1578 additions and 58 deletions
|
|
@ -36,6 +36,7 @@
|
|||
#include "hw/misc/aspeed_lpc.h"
|
||||
#include "hw/misc/unimp.h"
|
||||
#include "hw/misc/aspeed_peci.h"
|
||||
#include "hw/fsi/aspeed_apb2opb.h"
|
||||
#include "hw/char/serial.h"
|
||||
|
||||
#define ASPEED_SPIS_NUM 2
|
||||
|
|
@ -90,6 +91,7 @@ struct AspeedSoCState {
|
|||
UnimplementedDeviceState udc;
|
||||
UnimplementedDeviceState sgpiom;
|
||||
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
|
||||
AspeedAPB2OPBState fsi[2];
|
||||
};
|
||||
|
||||
#define TYPE_ASPEED_SOC "aspeed-soc"
|
||||
|
|
@ -128,7 +130,8 @@ struct AspeedSoCClass {
|
|||
DeviceClass parent_class;
|
||||
|
||||
const char *name;
|
||||
const char *cpu_type;
|
||||
/** valid_cpu_types: NULL terminated array of a single CPU type. */
|
||||
const char * const *valid_cpu_types;
|
||||
uint32_t silicon_rev;
|
||||
uint64_t sram_size;
|
||||
uint64_t secsram_size;
|
||||
|
|
@ -143,6 +146,7 @@ struct AspeedSoCClass {
|
|||
qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
|
||||
};
|
||||
|
||||
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
|
||||
|
||||
enum {
|
||||
ASPEED_DEV_SPI_BOOT,
|
||||
|
|
@ -214,6 +218,8 @@ enum {
|
|||
ASPEED_DEV_SGPIOM,
|
||||
ASPEED_DEV_JTAG0,
|
||||
ASPEED_DEV_JTAG1,
|
||||
ASPEED_DEV_FSI1,
|
||||
ASPEED_DEV_FSI2,
|
||||
};
|
||||
|
||||
#define ASPEED_SOC_SPI_BOOT_ADDR 0x0
|
||||
|
|
|
|||
46
include/hw/fsi/aspeed_apb2opb.h
Normal file
46
include/hw/fsi/aspeed_apb2opb.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
* Copyright (C) 2024 IBM Corp.
|
||||
*
|
||||
* ASPEED APB2OPB Bridge
|
||||
* IBM On-Chip Peripheral Bus
|
||||
*/
|
||||
#ifndef FSI_ASPEED_APB2OPB_H
|
||||
#define FSI_ASPEED_APB2OPB_H
|
||||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/fsi/fsi-master.h"
|
||||
#include "hw/sysbus.h"
|
||||
|
||||
#define TYPE_FSI_OPB "fsi.opb"
|
||||
|
||||
#define TYPE_OP_BUS "opb"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(OPBus, OP_BUS)
|
||||
|
||||
typedef struct OPBus {
|
||||
BusState bus;
|
||||
|
||||
MemoryRegion mr;
|
||||
AddressSpace as;
|
||||
} OPBus;
|
||||
|
||||
#define TYPE_ASPEED_APB2OPB "aspeed.apb2opb"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(AspeedAPB2OPBState, ASPEED_APB2OPB)
|
||||
|
||||
#define ASPEED_APB2OPB_NR_REGS ((0xe8 >> 2) + 1)
|
||||
|
||||
#define ASPEED_FSI_NUM 2
|
||||
|
||||
typedef struct AspeedAPB2OPBState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion iomem;
|
||||
|
||||
uint32_t regs[ASPEED_APB2OPB_NR_REGS];
|
||||
qemu_irq irq;
|
||||
|
||||
OPBus opb[ASPEED_FSI_NUM];
|
||||
FSIMasterState fsi[ASPEED_FSI_NUM];
|
||||
} AspeedAPB2OPBState;
|
||||
|
||||
#endif /* FSI_ASPEED_APB2OPB_H */
|
||||
34
include/hw/fsi/cfam.h
Normal file
34
include/hw/fsi/cfam.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
* Copyright (C) 2024 IBM Corp.
|
||||
*
|
||||
* IBM Common FRU Access Macro
|
||||
*/
|
||||
#ifndef FSI_CFAM_H
|
||||
#define FSI_CFAM_H
|
||||
|
||||
#include "exec/memory.h"
|
||||
|
||||
#include "hw/fsi/fsi.h"
|
||||
#include "hw/fsi/lbus.h"
|
||||
|
||||
#define TYPE_FSI_CFAM "cfam"
|
||||
#define FSI_CFAM(obj) OBJECT_CHECK(FSICFAMState, (obj), TYPE_FSI_CFAM)
|
||||
|
||||
/* P9-ism */
|
||||
#define CFAM_CONFIG_NR_REGS 0x28
|
||||
|
||||
typedef struct FSICFAMState {
|
||||
/* < private > */
|
||||
FSISlaveState parent;
|
||||
|
||||
/* CFAM config address space */
|
||||
MemoryRegion config_iomem;
|
||||
|
||||
MemoryRegion mr;
|
||||
|
||||
FSILBus lbus;
|
||||
FSIScratchPad scratchpad;
|
||||
} FSICFAMState;
|
||||
|
||||
#endif /* FSI_CFAM_H */
|
||||
32
include/hw/fsi/fsi-master.h
Normal file
32
include/hw/fsi/fsi-master.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
* Copyright (C) 2024 IBM Corp.
|
||||
*
|
||||
* IBM Flexible Service Interface Master
|
||||
*/
|
||||
#ifndef FSI_FSI_MASTER_H
|
||||
#define FSI_FSI_MASTER_H
|
||||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/qdev-core.h"
|
||||
#include "hw/fsi/fsi.h"
|
||||
#include "hw/fsi/cfam.h"
|
||||
|
||||
#define TYPE_FSI_MASTER "fsi.master"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER)
|
||||
|
||||
#define FSI_MASTER_NR_REGS ((0x2e0 >> 2) + 1)
|
||||
|
||||
typedef struct FSIMasterState {
|
||||
DeviceState parent;
|
||||
MemoryRegion iomem;
|
||||
MemoryRegion opb2fsi;
|
||||
|
||||
FSIBus bus;
|
||||
|
||||
uint32_t regs[FSI_MASTER_NR_REGS];
|
||||
FSICFAMState cfam;
|
||||
} FSIMasterState;
|
||||
|
||||
|
||||
#endif /* FSI_FSI_H */
|
||||
37
include/hw/fsi/fsi.h
Normal file
37
include/hw/fsi/fsi.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
* Copyright (C) 2024 IBM Corp.
|
||||
*
|
||||
* IBM Flexible Service Interface
|
||||
*/
|
||||
#ifndef FSI_FSI_H
|
||||
#define FSI_FSI_H
|
||||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/qdev-core.h"
|
||||
#include "hw/fsi/lbus.h"
|
||||
#include "qemu/bitops.h"
|
||||
|
||||
/* Bitwise operations at the word level. */
|
||||
#define BE_GENMASK(hb, lb) MAKE_64BIT_MASK((lb), ((hb) - (lb) + 1))
|
||||
|
||||
#define TYPE_FSI_BUS "fsi.bus"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(FSIBus, FSI_BUS)
|
||||
|
||||
typedef struct FSIBus {
|
||||
BusState bus;
|
||||
} FSIBus;
|
||||
|
||||
#define TYPE_FSI_SLAVE "fsi.slave"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(FSISlaveState, FSI_SLAVE)
|
||||
|
||||
#define FSI_SLAVE_CONTROL_NR_REGS ((0x40 >> 2) + 1)
|
||||
|
||||
typedef struct FSISlaveState {
|
||||
DeviceState parent;
|
||||
|
||||
MemoryRegion iomem;
|
||||
uint32_t regs[FSI_SLAVE_CONTROL_NR_REGS];
|
||||
} FSISlaveState;
|
||||
|
||||
#endif /* FSI_FSI_H */
|
||||
43
include/hw/fsi/lbus.h
Normal file
43
include/hw/fsi/lbus.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
* Copyright (C) 2024 IBM Corp.
|
||||
*
|
||||
* IBM Local bus and connected device structures.
|
||||
*/
|
||||
#ifndef FSI_LBUS_H
|
||||
#define FSI_LBUS_H
|
||||
|
||||
#include "hw/qdev-core.h"
|
||||
#include "qemu/units.h"
|
||||
#include "exec/memory.h"
|
||||
|
||||
#define TYPE_FSI_LBUS_DEVICE "fsi.lbus.device"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(FSILBusDevice, FSI_LBUS_DEVICE)
|
||||
|
||||
typedef struct FSILBusDevice {
|
||||
DeviceState parent;
|
||||
|
||||
MemoryRegion iomem;
|
||||
} FSILBusDevice;
|
||||
|
||||
#define TYPE_FSI_LBUS "fsi.lbus"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(FSILBus, FSI_LBUS)
|
||||
|
||||
typedef struct FSILBus {
|
||||
BusState bus;
|
||||
|
||||
MemoryRegion mr;
|
||||
} FSILBus;
|
||||
|
||||
#define TYPE_FSI_SCRATCHPAD "fsi.scratchpad"
|
||||
#define SCRATCHPAD(obj) OBJECT_CHECK(FSIScratchPad, (obj), TYPE_FSI_SCRATCHPAD)
|
||||
|
||||
#define FSI_SCRATCHPAD_NR_REGS 4
|
||||
|
||||
typedef struct FSIScratchPad {
|
||||
FSILBusDevice parent;
|
||||
|
||||
uint32_t regs[FSI_SCRATCHPAD_NR_REGS];
|
||||
} FSIScratchPad;
|
||||
|
||||
#endif /* FSI_LBUS_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue