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riscv: zicond: make non-experimental
zicond is now codegen supported in both llvm and gcc. This change allows seamless enabling/testing of zicond in downstream projects. e.g. currently riscv-gnu-toolchain parses elf attributes to create a cmdline for qemu but fails short of enabling it because of the "x-" prefix. Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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1 changed files with 1 additions and 1 deletions
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@ -1869,6 +1869,7 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
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DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
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DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
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DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
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DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
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DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
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DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
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/* Vendor-specific custom extensions */
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/* Vendor-specific custom extensions */
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DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
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DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
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@ -1885,7 +1886,6 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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/* These are experimental so mark with 'x-' */
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/* These are experimental so mark with 'x-' */
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DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
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/* ePMP 0.9.3 */
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/* ePMP 0.9.3 */
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DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
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DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
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